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| preliminary datasheet specifications in this document are tentative and subject to change. rl78/g1a renesas mcu combines multi-channel 12-bit a/d converter, true low power platform (as low as 66 a/mhz, and 0.57 a for rtc + lvd), 1.6 v to 3.6 v operation, 16 to 64 kbyte flash, 41 dmips at 32 mhz page 1 of 76 r01ds0151ej0001 rev.0.01 2011.12.26 r01ds0151ej0001 rev.0.01 2011.12.26 1. outline 1.1 features ultra-low power technology ? 1.6 v to 3.6 v operation from a single supply ? stop (ram retained): 0.23 a, (lvd enabled): 0.31 a ? halt (rtc + lvd): 0.57 a ? snooze: t.b.d. ? operating: 66 a/mhz 16-bit rl78 cpu core ? delivers 41 dmips at maximum operating frequency of 32 mhz ? instruction execution: 86% of instructions can be executed in 1 to 2 clock cycles ? cisc architecture (harvard) with 3-stage pipeline ? multiply signed & unsigned: 16 x 16 to 32-bit result in 1 clock cycle ? mac: 16 x 16 to 32-bit result in 2 clock cycles ? 16-bit barrel shifter for shi ft & rotate in 1 clock cycle ? 1-wire on-chip debug function code flash memory ? density: 16 kb to 64 kb ? block size: 1 kb ? on-chip single voltage flash memory with protection from block erase/writing ? self-programming with secure boot swap function and flash shield window function data flash memory ? data flash with background operation ? data flash size: 4 kb ? erase cycles: 1 million (typ.) ? erase/programming voltage: 1.8 v to 3.6 v ram ? 2 kb to 4 kb size options ? supports operands or instructions ? back-up retention in all modes high-speed on-chip oscillator ? 32 mhz with +/ ? 1% accuracy over voltage (1.8 v to 3.6 v) and temperature ( ? 20 c to +85 c) ? pre-configured settings: 32 mhz, 24 mhz, 16 mhz, 12 mhz, 8 mhz, 4 mhz & 1 mhz reset and supply management ? power-on reset (por) monitor/generator ? low voltage detection (lvd) with 12 setting options (interrupt and/or reset function) data memory access (dma) controller ? up to 2 fully programmable channels ? transfer unit: 8- or 16-bit multiple communication interfaces ? up to 6 x i 2 c master ? up to 1 x i 2 c multi-master ? up to 6 x csi/spi (7-, 8-bit) ? up to 3 x uart (7-, 8-, 9-bit) ? up to 1 x lin extended-function timers ? multi-function 16-bit timers: up to 8 channels ? real-time clock (rtc): 1 channel (full calendar and alarm function with watch correction function) ? interval timer: 12-bit, 1 channel ? 15 khz watchdog timer: 1 channel (window function) rich analog ? adc: up to 28 channels, 12-bit resolution, 3.375 s conversion time ? supports 1.6 v ? internal voltage reference (1.45 v) ? on-chip temperature sensor safety features (iec or ul 60730 compliance) ? flash memory crc calculation ? ram parity error check ? ram write protection ? sfr write protection ? illegal memory access detection ? clock stop/ frequency detection ? adc self-test general purpose i/o ? 3.6 v tolerant, high-current (up to 20 ma per pin) ? open-drain, internal pull-up support operating ambient temperature ? standard: ? 40 c to +85 c package type and pin count from 3 mm x 3 mm to 10 mm x 10 mm qfp: 48, 64 qfn: 32, 48 lga: 25 bga: 64
rl78/g1a 1. outline page 2 of 76 r01ds0151ej0001 rev.0.01 2011.12.26 under development preliminary document specifications in this document are tentative and subject to change. { rom, ram capacities rl78/g1a flash rom data flash ram 25 pins 32 pins 48 pins 64 pins 64 kb 4 kb 4 kb note r5f10e8e r5f10ebe r5f10ege r5f10ele 48 kb 4 kb 3 kb r5f10e8d r5f10ebd r5f10egd r5f10eld 32 kb 4 kb 2 kb r5f10e8c r5f10ebc r5f10egc r5f10elc 16 kb 4 kb 2 kb r5f10e8a r5f10eba r5f10ega ? note this is about 3 kb when the self-programming function and data flash function are used. rl78/g1a 1. outline page 3 of 76 r01ds0151ej0001 rev.0.01 2011.12.26 under development preliminary document specifications in this document are tentative and subject to change. 1.2 ordering information ? flash memory version (lead-free product) pin count package data flash part number 25 pins 25-pin plastic flga (3 3) mounted r5f10e8aala, r5f10e8cala, r5f10e8dala, r5f10e8eala 32 pins 32-pin plastic wqfn (fine pitch) (5 5) mounted r5f10ebaana, r5f10ebcana, r5f10ebdana, r5f10ebeana 48-pin plastic lqfp (fine pitch) (7 7) mounted r5f10egaafb, r5f10egcafb, r5f10egdafb, R5F10EGEAFB 48 pins 48-pin plastic wqfn (7 7) mounted r5f10egaana, r5f10egcana, r5f10egdana, r5f10egeana 64-pin plastic lqfp (fine pitch) (10 10) mounted r5f10elcafb, r5f10eldafb, r5f10eleafb 64 pins 64-pin plastic fbga (4 4) mounted r5f10elcabg, r5f10eldabg, r5f10eleabg rl78/g1a 1. outline page 4 of 76 r01ds0151ej0001 rev.0.01 2011.12.26 under development preliminary document specifications in this document are tentative and subject to change. 1.3 pin configuration (top view) 1.3.1 25-pin products ? 25-pin plastic flga (3 3) index mark top view bottom view 5 4 3 2 1 abcde edcba index mark a b c d e 5 p40/tool0 reset p03/ani16/ rxd1/to00/ (kr1) p23/ani3/ (kr3) av ss 5 4 p122/x2/ exclk p137/intp0 p02/ani17/ txd1/ti00/ (kr0) p22/ani2/ (kr2) av dd 4 3 p121/x1 v dd p21/ani1/ av refm p11/ani20/ si00/sda00/ rxd0/ toolrxd p10/ani18/ sck00/scl00 3 2 regc v ss p30/ani27/ sck11/scl11/ intp3 p51/ani25/ so11/intp2 p50/ani26/ si11/sda11 intp1 2 1 p60/scla0 p61/sdaa0 p31/ani29/ti03/ to03/pclbuz0 /intp4 p12/ani21/ so00/txd0/ tooltxd p20/ani0/ av refp 1 a b c d e caution connect the regc pin to vss via a capacitor (0.47 to 1 f). remarks 1. for pin identification, see 1.4 pin identification . 2. functions in parentheses in the above figure can be assigned via setting s in the peripheral i/o redirection register (pior). rl78/g1a 1. outline page 5 of 76 r01ds0151ej0001 rev.0.01 2011.12.26 under development preliminary document specifications in this document are tentative and subject to change. 1.3.2 32-pin products ? 32-pin plastic wqfn (fine pitch) (5 5) 16 15 14 13 12 11 10 9 25 26 27 28 29 30 31 32 24 23 22 21 20 19 18 17 1 2 3 4 5 6 7 8 p24/ani4/(kr5) p23/ani3/ (kr4) p22/ani2/ (kr3) p21/ani1 /av refm p20/ani0 /av refp p03/ani16/rxd1/to00/(kr2) p02/ani17/txd1/ti00/(kr1) p120/ani19/(kr0) p51/so11/intp2 p50/ani26/si11/sda11/intp1 p30/ani27/sck11/scl11/intp3 p70/ani28/kr0 p31/ani29/ti03/to03/pclbuz0/intp4 p62 p61/sdaa0 p60/scla0 exposed die pad av ss av dd p10/ani18/sck00/scl00/(kr0) p11/ani20/si00/sda00/rxd0/toolrxd/(kr1) p12/ani21/so00/txd0/tooltxd/(kr2) p13/ani22/so20/txd2/(kr3) p14/ani23/si20/sda20/rxd2/(kr4) p15/ani24/sck20/scl20/pclbuz1/(kr5) p40/tool0 reset p137/intp0 p122/x2/exclk p121/x1 regc v ss v dd caution connect the regc pin to vss via a capacitor (0.47 to 1 f). remarks 1. for pin identification, see 1.4 pin identification . 2. functions in parentheses in the above figure can be assigned via setting s in the peripheral i/o redirection register (pior). rl78/g1a 1. outline page 6 of 76 r01ds0151ej0001 rev.0.01 2011.12.26 under development preliminary document specifications in this document are tentative and subject to change. 1.3.3 48-pin products ? 48-pin plastic lqfp (fine pitch) (7 7) 36 35 34 33 32 31 30 29 28 27 26 25 1 2 3 4 5 6 7 8 9 10 11 12 37 38 39 40 41 42 43 44 45 46 47 48 24 23 22 21 20 19 18 17 16 15 14 13 p120/ani19 p41/ani30/ti07/to07 p40/tool0 reset p124/xt2/exclks p123/xt1 p137/intp0 p122/x2/exclk p121/x1 regc v ss v dd p140/pclbuz0/intp6 p02/ani17/txd1/ti00/(kr0) p03/ani16/rxd1/to00/(kr1) p130 p20/ani0/av refp p21/ani1/av refm p22/ani2/(kr2) p23/ani3/(kr3) p24/ani4/(kr4) p25/ani5/(kr5) p26/ani6 p27/ani7 av ss av dd p150/ani8 p10/ani18/sck00/scl00/(kr0) p11/ani20/si00/sda00/rxd0/toolrxd/(kr1) p12/ani21/so00/txd0/tooltxd/(kr2) p13/ani22/so20/txd2/(kr3) p14/ani23/si20/sda20/rxd2/(kr4) p15/ani24/sck20/scl20/pclbuz1/(kr5) p16/ti01/to01/intp5 p51/ani25/so11/intp2 p50/ani26/si11/sda11/intp1 p60/scla0 p61/sdaa0 p62 p63 p31/ani29/ti03/to03/intp4 p75/sck01/scl01/intp9/kr5 p74/si01/sda01/intp8/kr4 p73/so01/kr3 p72/so21/kr2 p71/si21/sda21/kr1 p70/ani28/sck21/scl21/kr0 p30/ani27/sck11/scl11/intp3/rtc1hz caution connect the regc pin to vss via a capacitor (0.47 to 1 f). remarks 1. for pin identification, see 1.4 pin identification . 2. functions in parentheses in the above figure can be assigned via setting s in the peripheral i/o redirection register (pior). rl78/g1a 1. outline page 7 of 76 r01ds0151ej0001 rev.0.01 2011.12.26 under development preliminary document specifications in this document are tentative and subject to change. ? 48-pin plastic wqfn (7 7) 36 35 34 33 32 31 30 29 28 27 26 25 1 2 3 4 5 6 7 8 9 10 11 12 37 38 39 40 41 42 43 44 45 46 47 48 24 23 22 21 20 19 18 17 16 15 14 13 p120/ani19 p41/ani30/ti07/to07 p40/tool0 reset p124/xt2/exclks p123/xt1 p137/intp0 p122/x2/exclk p121/x1 regc v ss v dd p140/pclbuz0/intp6 p02/ani17/txd1/ti00/(kr0) p03/ani16/rxd1/to00/(kr1) p130 p20/ani0/av refp p21/ani1/av refm p22/ani2/(kr2) p23/ani3/(kr3) p24/ani4/(kr4) p25/ani5/(kr5) p26/ani6 p27/ani7 av ss av dd p150/ani8 p10/ani18/sck00/scl00/(kr0) p11/ani20/si00/sda00/rxd0/toolrxd/(kr1) p12/ani21/so00/txd0/tooltxd/(kr2) p13/ani22/so20/txd2/(kr3) p14/ani23/si20/sda20/rxd2/(kr4) p15/ani24/sck20/scl20/pclbuz1/(kr5) p16/ti01/to01/intp5 p51/ani25/so11/intp2 p50/ani26/si11/sda11/intp1 p60/scla0 p61/sdaa0 p62 p63 p31/ani29/ti03/to03/intp4 p75/sck01/scl01/intp9/kr5 p74/si01/sda01/intp8/kr4 p73/so01/kr3 p72/so21/kr2 p71/si21/sda21/kr1 p70/ani28/sck21/scl21/kr0 p30/ani27/sck11/scl11/intp3/rtc1hz caution connect the regc pin to vss via a capacitor (0.47 to 1 f). remarks 1. for pin identification, see 1.4 pin identification . 2. functions in parentheses in the above figure can be assigned via setting s in the peripheral i/o redirection register (pior). rl78/g1a 1. outline page 8 of 76 r01ds0151ej0001 rev.0.01 2011.12.26 under development preliminary document specifications in this document are tentative and subject to change. 1.3.4 64-pin products ? 64-pin plastic lqfp (fine pitch) (10 10) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 p27/ani7 p26/ani6/(kr9) p25/ani5/(kr8) p24/ani4/(kr7) p23/ani3/(kr6) p22/ani2/(kr5) p21/ani1/av refm p20/ani0/av refp p130 p04/sck10/scl10/(kr4) p03/ani16/si10/sda10/rxd1/(kr3) p02/ani17/so10/txd1/(kr2) p01/to00/(kr1) p00/ti00/(kr0) p141/pclbuz1/intp7 p140/pclbuz0/intp6 p30/ani27/sck11/scl11/intp3/rtc1hz p05/ti05/to05/kr8 p06/ti06/to06/kr9 p70/ani28/sck21/scl21/kr0 p71/si21/sda21/kr1 p72/so21/kr2 p73/so01/kr3 p74/si01/sda01/intp8/kr4 p75/sck01/scl01/intp9/kr5 p76/intp10/kr6 p77/intp11/kr7 p31/ani29/ti03/to03/intp4 p63 p62 p61/sdaa0 p60/scla0 av ss av dd p150/ani8 p151/ani9/(kr6) p152/ani10/(kr7) p153/ani11/(kr8) p154/ani12/(kr9) p10/ani18/sck00/scl00/(kr0) p11/ani20/si00/sda00/rxd0/toolrxd/(kr1) p12/ani21/so00/txd0/tooltxd/(kr2) p13/ani22/so20/txd2/(kr3) p14/ani23/si20/sda20/rxd2/(kr4) p15/ani24/sck20/scl20/(kr5) p16/ti01/to01/intp5 p51/ani25/so11/intp2 p50/ani26/si11/sda11/intp1 p120/ani19 p43 p42/ti04/to04 p41/ani30/ti07/to07 p40/tool0 reset p124/xt2/exclks p123/xt1 p137/intp0 p122/x2/exclk p121/x1 regc v ss ev ss0 v dd ev dd0 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 cautions 1. make ev ss0 pin the same potential as v ss pin. 2. make v dd pin the potential that is higher than ev dd0 pin. 3. connect the regc pin to vss via a capacitor (0.47 to 1 f). remarks 1. for pin identification, see 1.4 pin identification. 2. when using the microcontroller for an applicat ion where the noise generated inside the microcontroller must be reduced, it is reco mmended to supply separate powers to the v dd and ev dd0 pins and connect the v ss and ev ss 0pins to separate ground lines. 3. functions in parentheses in the above figure can be assigned via settings in the peripheral i/o redirection register (pior). rl78/g1a 1. outline page 9 of 76 r01ds0151ej0001 rev.0.01 2011.12.26 under development preliminary document specifications in this document are tentative and subject to change. ? 64-pin plastic fbga (4 4) 1 hgfedcba 2 3 4 5 6 7 8 abcdefgh top view bottom view index mark pin no. name pin no. name pin no. name pin no. name a1 p05/ti05/to05/kr8 c1 p51/ani25/so11 /intp2 e1 p153/ani11/(kr8) g1 av dd a2 p30/ani27/sck11 /scl11/intp3 /rtc1hz c2 p71/si21/sda21/kr1 e2 p154/ani12/(kr9) g2 p25/ani5/(kr8) a3 p70/ani28/sck21 /scl21/kr0 c3 p74/si01/sda01 /intp8/kr4 e3 p10/ani18/sck00 /scl00/(kr0) g3 p24/ani4/(kr7) a4 p75/sck01/scl01 /intp9/kr5 c4 p16/ti01/to01/intp5 e4 p11/ani20/si00 /sda00/rxd0 /toolrxd/(kr1) g4 p22/ani2/(kr5) a5 p77/intp11/kr7 c5 p15/ani24/sck20 /scl20/(kr5) e5 p03/ani16/si10 /sda10/rxd1/(kr3) g5 p130 a6 p61/sdaa0 c6 p63 e6 p41/ani30/ti07/to07 g6 p02/ani17/so10/txd1 /(kr2) a7 p60/scla0 c7 v ss e7 reset g7 p00/ti00/(kr0) a8 ev dd0 c8 p121/x1 e8 p137/intp0 g8 p124/xt2/exclks b1 p50/ani26 /si11 /sda11/intp1 d1 p13/ani22/so20 /txd2/(kr3) f1 p150/ani8 h1 av ss b2 p72/so21/kr2 d2 p06/ti06/to06/kr9 f2 p151/ani9/(kr6) h2 p27/ani7 b3 p73/so01/kr3 d3 p12/ani21/so00 /txd0/tooltxd/(kr2) f3 p152/ani10/(kr7) h3 p26/ani6/(kr9) b4 p76/intp10/kr6 d4 p14/ani23/si20/ sda20/rxd2/(kr4) f4 p21/ani1/av refm h4 p23/ani3/(kr6) b5 p31/ani29/ti03/to03 /intp4 d5 p42/ti04/to04 f5 p04/sck10/scl10 /(kr4) h5 p20/ani0/av refp b6 p62 d6 p40/tool0 f6 p43 h6 p141/pclbuz1/intp7 b7 v dd d7 regc f7 p01/to00/(kr1) h7 p140/pclbuz0/intp6 b8 ev ss0 d8 p122/x2/exclk f8 p123/xt1 h8 p120/ani19 cautions 1. make ev ss0 pin the same potential as v ss pin. 2. make v dd pin the potential that is higher than ev dd0 pin. 3. connect the regc pin to vss via a capacitor (0.47 to 1 f). remarks 1. for pin identification, see 1.4 pin identification. 2. when using the microcontroller for an appl ication where the no ise generated inside the microcontroller must be reduced, it is reco mmended to supply separate powers to the v dd and ev dd0 pins and connect the v ss and ev ss0 pins to separate ground lines. 3. functions in parentheses in the above figure can be assigned via settings in the peripheral i/o redirection register (pior). rl78/g1a 1. outline page 10 of 76 r01ds0151ej0001 rev.0.01 2011.12.26 under development preliminary document specifications in this document are tentative and subject to change. 1.4 pin identification ani0 to ani12, ani16 to ani30: analog input av dd : analog power supply av ss : analog ground av refm : a/d converter reference potential ( ? side) input av refp : a/d converter reference potential (+ side) input ev dd0 : power supply for port ev ss0 : ground for port exclk: external clock input (main system clock) exclks: external clock input (sub system clock) intp0 to intp11: external interrupt input kr0 to kr9: key return p00 to p06: port 0 p10 to p16: port 1 p20 to p27: port 2 p30, p31: port 3 p40 to p43: port 4 p50, p51: port 5 p60 to p63: port 6 p70 to p77: port 7 p120 to p124: port 12 p130, p137: port 13 p140, p141: port 14 p150 to p154: port 15 pclbuz0, pclbuz1: programmable clock output/buzzer output regc: regulator capacitance reset: reset rtc1hz: real-time cloc k correction clock (1 hz) output rxd0 to rxd2: receive data sck00, sck01, sck10, sck11, sck20, sck21: serial clock input/output scla0, scl00, scl01, scl10, scl11, scl20, scl21: serial clock input/output sdaa0, sda00, sda01, sda10, sda11, sda20, sda21: serial data input/output si00, si01, si10, si11, si20, si21: serial data input so00, so01, so10, so11, so20, so21: serial data output ti00, ti01, ti03 to ti07: timer input to00, to01, to03 to to07: timer output tool0: data input/output for tool toolrxd, tooltxd: data inpu t/output for external device txd0 to txd2: transmit data v dd : power supply v ss : ground x1, x2: crystal oscillator (main system clock) xt1, xt2: crystal oscillator (subsystem clock) rl78/g1a 1. outline page 11 of 76 r01ds0151ej0001 rev.0.01 2011.12.26 under development preliminary document specifications in this document are tentative and subject to change. 1.5 block diagram 1.5.1 25-pin products port 1 p10 to p12 port 2 p20 to p23 4 port 3 p30, p31 2 port 4 port 5 3 port 12 p121, p122 p40 voltage regulator regc interrupt control ram power on reset/ voltage detector por/lvd control reset control system control reset x1/p121 x2/exclk/p122 high-speed on-chip oscillator on-chip debug tool0/p40 serial array unit0 (4ch) uart0 uart1 iic00 rxd0/p11 txd0/p12 rxd1/p03 txd1/p02 scl00/p10 sda00/p11 timer array unit (8ch) ch2 ch3 ti03/to03/p31 ch0 ch1 ch4 ch5 ch6 ch7 intp0/p137 intp3/p30, intp4/p31 intp1/p50 a/d converter 4 ani0/p20 to ani3/p23 av refp /p20 av refm /p21 2 port 13 p137 csi11 sck11/p30 so11/p51 si11/p50 iic11 scl11/p30 sda11/p50 ti00/p02 to00/p03 bcd adjustment sck00/p10 so00/p12 si00/p11 csi00 v ss av ss toolrxd/p11, tooltxd/p12 v dd av dd serial interface iica0 sdaa0/p61 scla0/p60 2 intp2/p51 multiplier& divider, mulitiply- accumulator port 0 p02, p03 2 9 ani16/p03, ani17/p02, ani18/p10, ani20/p11, ani21/p12, ani25/p51, ani26/p50, ani27/p30, ani29/p31 direct memory access control port 6 p60, p61 2 buzzer output pclbuz0/p31 clock output control window watchdog timer low-speed on-chip oscillator real-time clock rl78 cpu core code flash memory data flash memory interval timer key return kr0/p02 kr1/p03 kr2/p22 kr3/p23 p50, p51 2 (key return) (4) (kr0/p02, kr1/p03, kr2/p22, kr3/p23) remark functions in parentheses in the above figure can be assigned via settings in the peripheral i/o redirection register (pior). rl78/g1a 1. outline page 12 of 76 r01ds0151ej0001 rev.0.01 2011.12.26 under development preliminary document specifications in this document are tentative and subject to change. 1.5.2 32-pin products port 1 p10 to p15 port 2 p20 to p24 5 port 3 p30, p31 2 port 4 port 5 6 port 12 p121, p122 p40 p50, p51 2 voltage regulator regc interrupt control ram power on reset/ voltage detector por/lvd control reset control system control reset x1/p121 x2/exclk/p122 high-speed on-chip oscillator on-chip debug tool0/p40 serial array unit0 (4ch) uart0 uart1 iic00 rxd0/p11 txd0/p12 rxd1/p03 txd1/p02 scl00/p10 sda00/p11 timer array unit (8ch) ch2 ch3 ti03/to03/p31 ch0 ch1 ch4 ch5 ch6 ch7 2 intp0/p137 intp3/p30, intp4/p31 intp1/p50, intp2/p51 rxd2/p14 a/d converter 5 ani0/p20 to ani4/p24 av refp /p20 av refm /p21 2 p120 port 13 p137 csi11 sck11/p30 so11/p51 si11/p50 iic11 scl11/p30 sda11/p50 ti00/p02 to00/p03 bcd adjustment sck00/p10 so00/p12 si00/p11 csi00 v ss toolrxd/p11, tooltxd/p12 v dd serial interface iica0 sdaa0/p61 scla0/p60 2 multiplier& divider, mulitiply- accumulator port 0 p02, p03 2 buzzer output clock output control 13 ani16/p03, ani17/p02, ani18/p10, ani19/p120 to ani24/p15, ani26/p50, ani27/p30, ani28/p70, ani29/p31 serial array unit1 (2ch) uart2 linsel iic20 rxd2/p14 txd2/p13 scl20/p15 sda20/p14 sck20/p15 so20/p13 si20/p14 csi20 direct memory access control port 6 port 7 p70 p60 to p62 3 pclbuz0/p31, pclbuz1/p15 2 window watchdog timer low-speed on-chip oscillator real-time clock rl78 cpu core code flash memory data flash memory interval timer key return 1(6) kr0/p70 (kr0/p10 to kr5/p15) (kr0/p120, kr1/p02, kr2/p03, kr3/p22 to kr5/p24) rxd2/p14 remark functions in parentheses in the above figure can be assigned via settings in the peripheral i/o redirection register (pior). rl78/g1a 1. outline page 13 of 76 r01ds0151ej0001 rev.0.01 2011.12.26 under development preliminary document specifications in this document are tentative and subject to change. 1.5.3 48-pin products port 1 p10 to p16 port 2 p20 to p27 8 port 3 p30, p31 2 port 4 port 5 7 port 12 p121 to p124 p40, p41 2 p50, p51 2 voltage regulator regc interrupt control ram window watchdog timer low-speed on-chip oscillator power on reset/ voltage detector por/lvd control reset control system control reset x1/p121 x2/exclk/p122 high-speed on-chip oscillator on-chip debug tool0/p40 serial array unit0 (4ch) uart0 uart1 iic00 rxd0/p11 txd0/p12 rxd1/p03 txd1/p02 scl00/p10 sda00/p11 timer array unit (8ch) ch2 ti03/to03/p31 ch3 ch0 ch1 ch4 ch5 ch6 ch7 intp8/p74, intp9/p75 2 intp0/p137 intp3/p30, intp4/p31 intp6/p140 intp1/p50, intp2/p51 rxd2/p14 a/d converter 9 ani0/p20 to ani7/p27, ani8/p150 av refp /p20 av refm /p21 4 p120 port 13 p130 p137 csi11 sck11/p30 so11/p51 si11/p50 iic01 scl01/p75 sda01/p74 iic11 scl11/p30 sda11/p50 ti07/to07/p41 ti00/p02 to00/p03 bcd adjustment sck00/p10 so00/p12 si00/p11 csi00 v ss toolrxd/p11, tooltxd/p12 v dd serial interface iica0 sdaa0/p61 scla0/p60 2 2 intp5/p16 multiplier& divider, mulitiply- accumulator xt1/p123 xt2/exclks/p124 port 0 p02, p03 2 buzzer output pclbuz0/p140, pclbuz1/p15 clock output control key return 6(6) kr0/p70 to kr5/p75 (kr0/p10 to kr5/p15) (kr0/p02, kr1/p03 to kr5/p25) 15 ani16/p03, ani17/p02, ani18/p10, ani19/p120, ani20/p11 to ani24/p15, ani25/p51, ani26/p50, ani27/p30, ani28/p70, ani29/p31, ani30/p41 sck01/p75 so01/p73 si01/p74 csi01 serial array unit1 (2ch) uart2 linsel iic20 rxd2/p14 txd2/p13 scl20/p15 sda20/p14 iic21 scl21/p70 sda21/p71 sck20/p15 so20/p13 si20/p14 csi20 sck21/p70 so21/p72 si21/p71 csi21 direct memory access control port 6 port 7 p70 to p75 6 p60 to p63 4 port 14 p140 2 ti01/to01/p16 rtc1hz/p30 rxd2/p14 real-time clock rl78 cpu core code flash memory data flash memory interval timer port 15 p150 remark functions in parentheses in the above figure can be assigned via settings in the peripheral i/o redirection register (pior). rl78/g1a 1. outline page 14 of 76 r01ds0151ej0001 rev.0.01 2011.12.26 under development preliminary document specifications in this document are tentative and subject to change. 1.5.4 64-pin products port 2 p20 to p27 8 port 3 p30, p31 2 port 1 p10 to p16 7 port 4 p40 to p43 4 port 5 p50, p51 2 voltage regulator regc interrupt control ram rl78 cpu core window watchdog timer low-speed on-chip oscillator power on reset/ voltage detector por/lvd control reset control system control reset x1/p121 x2/exclk/p122 high-speed on-chip oscillator on-chip debug tool0/p40 serial array unit0 (4ch) uart0 uart1 iic00 rxd0/p11 txd0/p12 rxd1/p03 txd1/p02 scl00/p10 sda00/p11 timer array unit (8ch) ch2 ch3 ti03/to03/p31 ch0 ch1 ch4 ti04/to04/p42 ch5 ti05/to05/p05 ch6 ti06/to06/p06 ch7 intp8/p74, intp9/p75 2 intp0/p137 intp3/p30, intp4/p31 intp6/p140, intp7/p141 intp1/p50, intp2/p51 rxd2/p14 csi10 sck10/p04 so10/p02 si10/p03 a/d converter 13 ani0/p20 to ani7/p27, ani8/p150 to ani12/p154 av refp /p20 av refm /p21 port 12 p121 to p124 4 p120 port 13 p130 p137 csi11 sck11/p30 so11/p51 si11/p50 iic01 scl01/p75 sda01/p74 iic10 scl10/p04 sda10/p03 iic11 scl11/p30 sda11/p50 ti07/to07/p41 ti00/p00 to00/p01 bcd adjustment sck00/p10 so00/p12 si00/p11 csi00 v ss , ev ss0 toolrxd/p11, tooltxd/p12 v dd , ev dd0 serial interface iica0 sdaa0/p61 scla0/p60 2 2 2 intp5/p16 multiplier& divider, mulitiply- accumulator xt1/p123 xt2/exclks/p124 port 0 p00 to p06 7 buzzer output pclbuz0/p140, pclbuz1/p141 clock output control key return 10 (10) kr0/p70 to kr7/p77, kr8/p05, kr9/p06 (kr0/p00 to kr4/p04, kr5/p22 to kr9/p26) (kr0/p10 to kr5/p15, kr6/p151 to kr9/p154) 15 ani16/p03, ani17/p02, ani18/p10, ani19/p120, ani20/p11 to ani24/p15, ani25//p51, ani26/p50, ani27/p30, ani28/p70, ani29/p31, ani30/p41 sck01/p75 so01/p73 si01/p74 csi01 serial array unit1 (2ch) uart2 linsel iic20 rxd2/p14 txd2/p13 scl20/p15 sda20/p14 iic21 scl21/p70 sda21/p71 sck20/p15 so20/p13 si20/p14 csi20 sck21/p70 so21/p72 si21/p71 csi21 direct memory access control port 7 p70 to p77 8 port 6 p60 to p63 4 port 14 p140, p141 2 2 ti01/to01/p16 rtc1hz/p30 rxd2/p14 real-time clock code flash memory data flash memory interval timer intp10/p76, intp11/p77 2 port 15 p150 to p154 5 remark functions in parentheses in the above figure can be assigned via settings in the peripheral i/o redirection register (pior). rl78/g1a 1. outline page 15 of 76 r01ds0151ej0001 rev.0.01 2011.12.26 under development preliminary document specifications in this document are tentative and subject to change. 1.6 outline of functions (1/2) 25-pin 32-pin 48-pin 64-pin item r5f10e8x r5f10ebx r5f10egx r5f10elx code flash memory (kb) 16 to 64 16 to 64 16 to 64 32 to 64 data flash memory (kb) 4 4 4 4 ram (kb) 2 to 4 note1 2 to 4 note1 2 to 4 note1 2 to 4 note1 memory space 1 mb high-speed system clock x1 (crystal/ceramic) oscillation, extern al main system clock input (exclk) 1 to 20 mhz: v dd = 2.7 to 3.6 v, 1 to 8 mhz: v dd = 1.8 to 2.7 v, 1 to 4 mhz: v dd = 1.6 to 1.8 v main system clock high-speed on-chip oscillator high-speed operation: 1 to 32 mhz (v dd = 2.7 to 3.6 v), high-speed operation: 1 to 16 mhz (v dd = 2.4 to 3.6 v), low-speed operation: 1 to 8 mhz (v dd = 1.8 to 3.6 v), low-voltage operation: 1 to 4 mhz (v dd = 1.6 to 3.6 v) subsystem clock ? xt1 (crystal) oscillation, external subsystem clock input (exclks) 32.768 khz (typ.): v dd = 1.6 to 3.6 v low-speed on-chip oscillator 15 khz (typ.): v dd = 1.6 to 3.6 v general-purpose register 8 bits 32 registers (8 bits 8 registers 4 banks) 0.03125 s (high-speed on-chip oscillator: f ih = 32 mhz operation) 0.05 s (high-speed system clock: f mx = 20 mhz operation) minimum instruction execution time ? 30.5 s (subsystem clock: f sub = 32.768 khz operation) instruction set ? data transfer (8/16 bits) ? adder and subtractor/logical operation (8/16 bits) ? multiplication (8 bits 8 bits) ? rotate, barrel shift, and bit manipulation (s et, reset, test, and boolean operation), etc. i/o port total 19 26 42 56 cmos i/o 14 20 32 46 cmos input 3 3 5 5 cmos output ? ? 1 1 n-ch open-drain i/o (6 v tolerance) 2 3 4 4 16-bit timer 8 channels watchdog timer 1 channel timer real-time clock (rtc) ? 1 channel interval timer (it) 1 channel timer output 2 channels (pwm outputs: 1 note 2 ) 4 channels (pwm outputs: 3 note 2 ) 7 channels (pwm outputs: 6 note 2 ) rtc output ? 1 ? 1 hz (subsystem clock: f sub = 32.768 khz or ) notes 1. in the case of the 4 kb, this is about 3 kb when the self-programming function and data flash function are used. 2. the number of outputs vari es, depending on the setting. rl78/g1a 1. outline page 16 of 76 r01ds0151ej0001 rev.0.01 2011.12.26 under development preliminary document specifications in this document are tentative and subject to change. (2/2) 25-pin 32-pin 48-pin 64-pin item r5f10e8x r5f10ebx r5f10egx r5f10elx 1 2 2 2 clock output/buzzer output ? 2.44 khz, 4.88 khz, 9.76 khz, 1.25 mhz, 2.5 mhz, 5 mhz, 10 mhz (main system clock: f main = 20 mhz operation) ? 2.44 khz, 4.88 khz, 9.76 khz, 1.25 mhz, 2.5 mhz, 5 mhz, 10 mhz (main system clock: f main = 20 mhz operation) ? 256 hz, 512 hz, 1.024 khz, 2.048 khz, 4.096 khz, 8.192 khz, 16.384 khz, 32.768 khz (subsystem clock: f sub = 32.768 khz operation) 8/12-bit resolution a/d converter 13 c hannels 18 channels 24 channels 28 channels serial interface [25-pin products] ? csi: 1 channel/uart: 1 channel/simplified i 2 c: 1 channel ? csi: 1 channel/uart: 1 channel/simplified i 2 c: 1 channel [32-pin products] ? csi: 1 channel/uart: 1 channel/simplified i 2 c: 1 channel ? csi: 1 channel/uart: 1 channel/simplified i 2 c: 1 channel ? csi: 1 channel/uart (uart supporti ng lin-bus): 1 channel/simplified i 2 c: 1 channel [48-pin products] ? csi: 2 channels/uart: 1 channel/simplified i 2 c: 2 channels ? csi: 1 channel/uart: 1 channel/simplified i 2 c: 1 channel ? csi: 2 channels/uart (uart support ing lin-bus): 1 channel/simplified i 2 c: 2 channels [64-pin products] ? csi: 2 channels/uart: 1 channel/simplified i 2 c: 2 channels ? csi: 2 channels/uart: 1 channel/simplified i 2 c: 2 channels ? csi: 2 channels/uart (uart support ing lin-bus): 1 channel/simplified i 2 c: 2 channels i 2 c bus 1 channel 1 channel 1 channel 1 channel multiplier and divider/multipl y-accumulator ? 16 bits 16 bits = 32 bits (unsigned or signed) ? 32 bits 32 bits = 32 bits (unsigned) ? 16 bits 16 bits + 32 bits = 32 bits (unsigned or signed) dma controller 2 channels internal 24 27 27 27 vectored interrupt sources external 6 6 10 13 key interrupt 0 ch (4 ch) note 1 1 ch (6 ch) note 1 6 ch 10 ch reset ? reset by reset pin ? internal reset by watchdog timer ? internal reset by power-on-reset ? internal reset by voltage detector ? internal reset by illegal instruction execution note 2 ? internal reset by ram parity error ? internal reset by illegal-memory access power-on-reset circuit ? power-on-reset: 1.51 0.03 v ? power-down-reset: 1.50 0.03 v voltage detector 1.63 v to 3.06 v (12 stages) on-chip debug function provided power supply voltage v dd = 1.6 to 3.6 v operating ambient temperature t a = ? 40 to +85 c notes 1. can be used by the peripheral i/o redirection register (pior). 2. the illegal instruction is generated wh en instruction code ffh is executed. reset by the illegal instruction execution not issu ed by emulation with the in-circuit emulator or on-chip debug emulator. rl78/g1a 2. electrical specifications page 17 of 76 r01ds0151ej0001 rev.0.01 2011.12.26 under development preliminary document specifications in this document are tentative and subject to change. 2. electrical specifications cautions 1. these specifications show target values, which may change after device evaluation. 2. the rl78/g1a has an on-chip debug func tion, which is provided for development and evaluation. do not use the on-chip debug function in products designated for mass production, because the guaranteed number of re writable times of th e flash memory may be exceeded when this function is used, and product reliability therefore cannot be guaranteed. renesas electronics is not liabl e for problems occurri ng when the on-chip debug function is used. 3. the pins mounted depend on the product. re fer to 1.3.1 25-pin products to 1.3.4 64-pin products. rl78/g1a 2. electrical specifications page 18 of 76 r01ds0151ej0001 rev.0.01 2011.12.26 under development preliminary document specifications in this document are tentative and subject to change. caution the pins mounted depend on the product. refer to 1.3.1 25-pin products to 1.3.4 64-pin products. 2.1 absolute maximum ratings absolute maximum ratings (t a = 25 c) (1/2) parameter symbols conditions ratings unit v dd ? 0.5 to +6.5 v ev dd0 ev dd0 v dd ? 0.5 to +6.5 v av dd av dd0 v dd ? 0.5 to +4.6 v v ss ? 0.5 to +0.3 v ev ss0 ? 0.5 to +0.3 v supply voltage av ss ? 0.5 to +0.3 v regc pin input voltage v iregc regc ? 0.3 to +2.8 and ? 0.3 to v dd +0.3 note 1 v v i1 p00 to p06, p10 to p16, p30, p31, p40 to p43, p50, p51, p70 to p77, p120, p140, p141 ? 0.3 to ev dd0 +0.3 and ? 0.3 to v dd +0.3 note 2 v v i2 p60 to p63 (n-ch open-drain) ? 0.3 to +6.5 v v i3 p121 to p124, p137, exclk, exclks, reset ? 0.3 to v dd +0.3 note 2 v input voltage v i4 p20 to p27, p150 to p154 ? 0.3 to av dd +0.3 note 3 v v o1 p00 to p06, p10 to p16, p30, p31, p40 to p43, p50, p51, p60 to p63, p70 to p77, p120, p130, p140, p141 ? 0.3 to ev dd0 +0.3 note 2 v output voltage v o2 p20 to p27, p150 to p154 ? 0.3 to v dd +0.3 note 2 v v ai1 ani16 to ani30 ? 0.3 to ev dd0 +0.3 note 2 v analog input voltage v ai2 ani0 to ani12 ? 0.3 to av dd +0.3 note 2 v notes 1. connect the regc pin to vss via a capacitor (0.47 to 1 f). this value regulates the absolute maximum ratinwg of the regc pin. do not use this pin with voltage applied to it. 2. must be 6.5 v or lower. 3. must be 4.6 v or lower. caution product quality may suffer if the absolute maximum rating is exceeded even momentarily for any parameter. that is, the absolute maximum ratings are rated values at which the product is on the verge of suffering physical damage, and therefor e the product must be used under conditions that ensure that the absolute maximum rati ngs are not exceeded. remark unless specified otherwise, the characteristics of alte rnate-function pins are the same as those of the port pins. rl78/g1a 2. electrical specifications page 19 of 76 r01ds0151ej0001 rev.0.01 2011.12.26 under development preliminary document specifications in this document are tentative and subject to change. caution the pins mounted depend on the product. refer to 1.3.1 25-pin products to 1.3.4 64-pin products. absolute maximum ratings (t a = 25 c) (2/2) parameter symbols conditions ratings unit per pin p00 to p06, p10 to p16, p30, p31, p40 to p43, p50, p51, p70 to p77, p120, p130, p140, p141 ? 40 ma p00 to p04, p40 to p43, p120, p130, p140, p141 ? 70 ma i oh1 total of all pins ? 170 ma p05, p06, p10 to p16, p30, p31, p50, p51, p70 to p77, ? 100 ma per pin ? 0.1 ma output current, high i oh2 total of all pins p20 to p27, p150 to p154 ? 1.3 ma per pin p00 to p06, p10 to p16, p30, p31, p40 to p43, p50, p51, p60 to p63, p70 to p77, p120, p130, p140, p141 40 ma p00 to p04, p40 to p43, p120, p130, p140, p141 70 ma i ol1 total of all pins 170 ma p05, p06, p10 to p16, p30, p31, p50, p51, p60 to p63, p70 to p77 100 ma per pin 0.4 ma output current, low i ol2 total of all pins p20 to p27, p150 to p154 6.4 ma in normal operation mode operating ambient temperature t a in flash memory programming mode ? 40 to +85 c storage temperature t stg ? 65 to +150 c caution product quality may suffer if the absolute maximum rating is exceeded even momentarily for any parameter. that is, the absolute maximum ratings are rated values at which the product is on the verge of suffering physical damage, and therefor e the product must be used under conditions that ensure that the absolute maximum rati ngs are not exceeded. remark unless specified otherwise, the characteristics of alte rnate-function pins are the same as those of the port pins. rl78/g1a 2. electrical specifications page 20 of 76 r01ds0151ej0001 rev.0.01 2011.12.26 under development preliminary document specifications in this document are tentative and subject to change. caution the pins mounted depend on the product. refer to 1.3.1 25-pin products to 1.3.4 64-pin products. 2.2 oscillator characteristics 2.2.1 main system clock oscillator characteristics (t a = ? 40 to +85 c, 1.6 v ev dd0 v dd 3.6 v, v ss = ev ss0 = 0 v) resonator recommended circuit parameter conditions min. typ. max. unit 2.7 v v dd 3.6 v 1.0 20.0 mhz 1.8 v v dd < 2.7 v 1.0 8.0 mhz ceramic resonator c1 x2 x1 c2 v ss rd x1 clock oscillation frequency (f x ) note 1.6 v v dd < 1.8 v 1.0 4.0 mhz 2.7 v v dd 3.6 v 1.0 20.0 mhz 1.8 v v dd < 2.7 v 1.0 8.0 mhz crystal resonator c1 x2 x1 c2 v ss rd x1 clock oscillation frequency (f x ) note 1.6 v v dd < 1.8 v 1.0 4.0 mhz note indicates only oscillator characteri stics. refer to ac characterist ics for instruction execution time. cautions 1. when using the x1 oscillator, wire as follo ws in the area enclosed by the broken lines in the above figures to avoid an adverse effect from wiring capacitance. ? keep the wiring lengt h as short as possible. ? do not cross the wiring with the other signal lines. ? do not route the wiring near a signal line th rough which a high fluctuating current flows. ? always make the ground point of the o scillator capacitor the same potential as v ss . ? do not ground the capacitor to a ground pattern through which a high current flows. ? do not fetch signals from the oscillator. 2. since the cpu is started by the high-speed on-chip oscillator clo ck after a reset release, check the x1 clock oscillation st abilization time using the o scillation stabilization time counter status register (ostc) by the user. de termine the oscillation stabilization time of the ostc register and the oscillation stabilization ti me select register (o sts) after sufficiently evaluating the oscillation stabilization ti me with the resonator to be used. rl78/g1a 2. electrical specifications page 21 of 76 r01ds0151ej0001 rev.0.01 2011.12.26 under development preliminary document specifications in this document are tentative and subject to change. caution the pins mounted depend on the product. refer to 1.3.1 25-pin products to 1.3.4 64-pin products. 2.2.2 on-chip oscillator characteristics (t a = ? 20 to +85 c, 1.6 v ev dd0 v dd 3.6 v, v ss = ev ss0 = 0 v) oscillators parameters conditions min. typ. max. unit 32 mhz selected 31.68 32.00 32.32 mhz 24 mhz selected 23.76 24.00 24.24 mhz 16 mhz selected 15.84 16.00 16.16 mhz 12 mhz selected 11.88 12.00 12.12 mhz 8 mhz selected 7.92 8.00 8.08 mhz 4 mhz selected 3.96 4.00 4.04 mhz 1.8 v v dd 3.6 v 1 mhz selected 0.99 1.00 1.01 mhz 32 mhz selected 30.40 32.00 33.60 mhz 24 mhz selected 22.80 24.00 25.20 mhz 16 mhz selected 15.20 16.00 16.80 mhz 12 mhz selected 11.40 12.00 12.60 mhz 8 mhz selected 7.60 8.00 8.40 mhz 4 mhz selected 3.80 4.00 4.20 mhz high-speed on-chip oscillator clock frequency note f ih 1.6 v v dd < 1.8 v 1 mhz selected 0.95 1.00 1.05 mhz low-speed on-chip oscillator clock frequency f il 12.75 15 17.25 khz (t a = ? 40 to ? 20 c, 1.6 v ev dd0 v dd 3.6 v, v ss = ev ss0 = 0 v) oscillators parameters conditions min. typ. max. unit 32 mhz selected 31.52 32.00 32.48 mhz 24 mhz selected 23.64 24.00 24.36 mhz 16 mhz selected 15.76 16.00 16.24 mhz 12 mhz selected 11.82 12.00 12.18 mhz 8 mhz selected 7.88 8.00 8.12 mhz 4 mhz selected 3.94 4.00 4.06 mhz 1.8 v v dd 3.6 v 1 mhz selected 0.985 1.00 1.015 mhz 32 mhz selected 30.24 32.00 33.76 mhz 24 mhz selected 22.68 24.00 25.32 mhz 16 mhz selected 15.12 16.00 16.88 mhz 12 mhz selected 11.34 12.00 12.66 mhz 8 mhz selected 7.56 8.00 8.44 mhz 4 mhz selected 3.78 4.00 4.22 mhz high-speed on-chip oscillator clock frequency note f ih 1.6 v v dd < 1.8 v 1 mhz selected 0.945 1.00 1.055 mhz low-speed on-chip oscillator clock frequency f il 12.75 15 17.25 khz note this only indicates the oscillator characteristics. refer to ac characteristics for instruction execution time. rl78/g1a 2. electrical specifications page 22 of 76 r01ds0151ej0001 rev.0.01 2011.12.26 under development preliminary document specifications in this document are tentative and subject to change. caution the pins mounted depend on the product. refer to 1.3.1 25-pin products to 1.3.4 64-pin products. 2.2.3 subsystem clock oscillator characteristics (t a = ? 40 to +85 c, 1.6 v ev dd0 v dd 3.6 v, v ss = ev ss0 = 0 v) resonator recommended circuit items conditions min. typ. max. unit crystal resonator xt1 xt2 c4 c3 rd v ss xt1 clock oscillation frequency (f xt ) note 32 32.768 35 khz note indicates only oscillator characteristics. refer to ac characteristics for instruction execution time. cautions 1. when using the xt1 oscillator, wire as follo ws in the area enclosed by the broken lines in the above figures to avoid an adverse effect from wiring capacitance. ? keep the wiring lengt h as short as possible. ? do not cross the wiring with the other signal lines. ? do not route the wiring near a signal line th rough which a high fluctuating current flows. ? always make the ground point of the o scillator capacitor the same potential as v ss . ? do not ground the capacitor to a ground pattern through which a high current flows. ? do not fetch signals from the oscillator. 2. the xt1 oscillator is desi gned as a low-amplitude circuit for reducing power consumption, and is more prone to ma lfunction due to noise than the x1 oscillator. particular care is therefore required with the wiring meth od when the xt1 clock is used. rl78/g1a 2. electrical specifications page 23 of 76 r01ds0151ej0001 rev.0.01 2011.12.26 under development preliminary document specifications in this document are tentative and subject to change. caution the pins mounted depend on the product. refer to 1.3.1 25-pin products to 1.3.4 64-pin products. 2.3 dc characteristics 2.3.1 pin characteristics (t a = ? 40 to +85 c, 1.6 v ev dd0 v dd 3.6 v, v ss = ev ss0 = 0 v) items symbol conditions min. typ. max. unit per pin for p00 to p06, p10 to p16, p30, p31, p40 to p43, p50, p51, p70 to p77, p120, p130, p140, p141 1.6 v ev dd0 3.6 v ? 10.0 note 2 ma 2.7 v ev dd0 3.6 v ? 10.0 ma 1.8 v ev dd0 < 2.7 v ? 5.0 ma total of p00 to p04, p40 to p43, p120, p130, p140, p141 (when duty = 70% note 3 ) 1.6 v ev dd0 < 1.8 v ? 2.5 ma 2.7 v ev dd0 3.6 v ? 19.0 ma 1.8 v ev dd0 < 2.7 v ? 10.0 ma total of p05, p06, p10 to p16, p30, p31, p50, p51, p70 to p77, (when duty = 70% note 3 ) 1.6 v ev dd0 < 1.8 v ? 5.0 ma i oh1 total of all pins (when duty = 70% note 3 ) 1.6 v ev dd0 3.6 v ? 29.0 ma per pin for p20 to p27, p150 to p154 1.6 v av dd 3.6 v ? 0.1 note 2 ma output current, high note 1 i oh2 total of all pins (when duty = 70% note 3 ) 1.6 v av dd 3.6 v ? 1.3 ma notes 1 . value of current at which the device operation is guaranteed even if the current flows from the ev dd0 , v dd pins to an output pin. 2. however, do not exceed the total current value. 3. specification under conditions where the duty factor is 70%. the output current value that has changed t he duty ratio can be calculated with the following expression (when changing the duty factor from 70% to n%). ? total output current of pins = (i oh 0.7)/(n 0.01) rl78/g1a 2. electrical specifications page 24 of 76 r01ds0151ej0001 rev.0.01 2011.12.26 under development preliminary document specifications in this document are tentative and subject to change. caution the pins mounted depend on the product. refer to 1.3.1 25-pin products to 1.3.4 64-pin products. (t a = ? 40 to +85 c, 1.6 v av dd 3.6 v, 1.6 v ev dd0 v dd 3.6 v, v ss = ev ss0 = 0 v) items symbol conditions min. typ. max. unit per pin for p00 to p06, p10 to p16, p30, p31, p40 to p43, p50, p51, p70 to p77, p120, p130, p140, p141 20.0 note 2 ma per pin for p60 to p63 15.0 note 2 ma 2.7 v ev dd0 3.6 v 15.0 ma 1.8 v ev dd0 < 2.7 v 9.0 ma total of p00 to p04, p40 to p43, p120, p130, p140, p141 (when duty = 70% note 3 ) 1.6 v ev dd0 < 1.8 v 4.5 ma 2.7 v ev dd0 3.6 v 35.0 ma 1.8 v ev dd0 < 2.7 v 20.0 ma total of p05, p06, p10 to p16, p30, p31, p50, p51, p60 to p63, p70 to p77 (when duty = 70% note 3 ) 1.6 v ev dd0 < 1.8 v 10.0 ma i ol1 total of all pins (when duty = 70% note 3 ) 50.0 ma per pin for p20 to p27, p150 to p154 0.4 note 2 ma output current, low note 1 i ol2 total of all pins (when duty = 70% note 3 ) 1.6 v av dd 3.6 v 5.2 ma notes 1 . value of current at which the device operation is guaranteed even if the current flows from an output pin to the ev ss0 and v ss pin. 2. however, do not exceed the total current value. 3. specification under conditions where the duty factor is 70%. the output current value that has changed t he duty ratio can be calculated with the following expression (when changing the duty factor from 70% to n%). ? total output current of pins = (i ol 0.7)/(n 0.01) rl78/g1a 2. electrical specifications page 25 of 76 r01ds0151ej0001 rev.0.01 2011.12.26 under development preliminary document specifications in this document are tentative and subject to change. caution the pins mounted depend on the product. refer to 1.3.1 25-pin products to 1.3.4 64-pin products. (t a = ? 40 to +85 c, 1.6 v av dd 3.6 v, 1.6 v ev dd0 v dd 3.6 v, v ss = ev ss0 = 0 v) items symbol conditions min. typ. max. unit v ih1 p00 to p06, p10 to p16, p30, p31, p40 to p43, p50, p51, p70 to p77, p120, p140, p141 normal input buffer 0.8ev dd0 ev dd0 v ttl input buffer 3.3 v ev dd0 < 3.6 v 2.0 ev dd0 v v ih2 p01, p03, p04, p10, p11, p13 to p16, p43 ttl input buffer 1.6 v ev dd0 < 3.3 v 1.5 ev dd0 v v ih3 p20 to p27, p150 to p154 0.7av dd av dd v v ih4 p60 to p63 0.7ev dd0 6.0 v input voltage, high v ih5 p121 to p124, p137, exclk, exclks, reset 0.8v dd v dd v v il1 p00 to p06, p10 to p16, p30, p31, p40 to p43, p50, p51, p70 to p77, p120, p140, p141 normal input buffer 0 0.2ev dd0 v ttl input buffer 3.3 v ev dd0 < 3.6 v 0 0.5 v v il2 p01, p03, p04, p10, p11, p13 to p16, p43 ttl input buffer 1.6 v ev dd0 < 3.3 v 0 0.32 v v il3 p20 to p27, p150 to p154 0 0.3av dd v v il4 p60 to p63 0 0.3ev dd0 v input voltage, low v il5 p121 to p124, p137, exclk, exclks, reset 0 0.2v dd v cautions 1. the maximum value of v ih of pins p00, p02 to p04, p10 to p15, p43, p50, p71, and p74 is ev dd0 , even in the n-ch open-drain mode. 2. always use av dd pin with the same potential as the v dd pin. remark unless specified otherwise, the charac teristics of alternate-function pi ns are the same as those of the port pins. rl78/g1a 2. electrical specifications page 26 of 76 r01ds0151ej0001 rev.0.01 2011.12.26 under development preliminary document specifications in this document are tentative and subject to change. caution the pins mounted depend on the product. refer to 1.3.1 25-pin products to 1.3.4 64-pin products. (t a = ? 40 to +85 c, 1.6 v av dd 3.6 v, 1.6 v ev dd0 v dd 3.6 v, v ss = ev ss0 = 0 v) items symbol conditions min. typ. max. unit 2.7 v ev dd0 3.6 v, i oh1 = ? 2.0 ma ev dd0 ? 0.6 v 1.8 v ev dd0 3.6 v, i oh1 = ? 1.5 ma ev dd0 ? 0.5 v v oh1 p00 to p06, p10 to p16, p30, p31, p40 to p43, p50, p51, p70 to p77, p120, p130, p140, p141 1.6 v ev dd0 < 3.6 v, i oh1 = ? 1.0 ma ev dd0 ? 0.5 v output voltage, high v oh2 p20 to p27, p150 to p154 1.6 v av dd 3.6 v, i oh2 = ? 100 a av dd ? 0.5 v 2.7 v ev dd0 3.6 v, i ol1 = 3.0 ma 0.6 v 2.7 v ev dd0 3.6 v, i ol1 = 1.5 ma 0.4 v 1.8 v ev dd0 3.6 v, i ol1 = 0.6 ma 0.4 v v ol1 p00 to p06, p10 to p16, p30, p31, p40 to p43, p50, p51, p70 to p77, p120, p130, p140, p141 1.6 v ev dd0 < 1.8 v, i ol1 = 0.3 ma 0.4 v v ol2 p20 to p27, p150 to p154 1.6 v av dd 3.6 v, i ol2 = 400 a 0.4 v 2.7 v ev dd0 3.6 v, i ol3 = 3.0 ma 0.4 v 1.8 v ev dd0 3.6 v, i ol3 = 2.0 ma 0.4 v output voltage, low v ol3 p60 to p63 1.6 v ev dd0 < 1.8 v, i ol3 = 1.0 ma 0.4 v caution 1. p00, p02 to p04, p10 to p15, p43, p50, p71, and p74 do not output high level in n-ch open-drain mode. 2. always use av dd pin with the same potential as the v dd pin. remark unless specified otherwise, the char acteristics of alternate-function pins are the same as those of the port pins. rl78/g1a 2. electrical specifications page 27 of 76 r01ds0151ej0001 rev.0.01 2011.12.26 under development preliminary document specifications in this document are tentative and subject to change. caution the pins mounted depend on the product. refer to 1.3.1 25-pin products to 1.3.4 64-pin products. (t a = ? 40 to +85 c, 1.6 v av dd 3.6 v, 1.6 v ev dd0 v dd 3.6 v, v ss = ev ss0 = 0 v) items symbol conditions min. typ. max. unit i lih1 p00 to p06, p10 to p16, p30, p31, p40 to p43, p50, p51, p60 to p63, p70 to p77, p120, p140, p141 v i = ev dd0 1 a i lih2 p20 to p27, p137, p150 to p154, reset v i = v dd 1 a in input port or external clock input 1 a i lih3 p121 to p124 (x1, x2, xt1, xt2, exclk, exclks) v i = v dd in resonator connection 10 a input leakage current, high i lih4 p20 to p27, p150 to p154 v i = av dd 1 a i lil1 p00 to p06, p10 to p16, p30, p31, p40 to p43, p50, p51, p60 to p67, p70 to p77, p120, p140, p141 v i = ev ss0 ? 1 a i lil2 p20 to p27, p137, p150 to p154, reset v i = v ss ? 1 a in input port or external clock input ? 1 a i lil3 p121 to p124 (x1, x2, xt1, xt2, exclk, exclks) v i = v ss in resonator connection ? 10 a input leakage current, low i lil4 p20 to p27, p150 to p154 v i = av ss ? 1 a on-chip pull-up resistance r u p00 to p06, p10 to p16, p30, p31, p40 to p43, p50, p51, p70 to p77, p120, p140, p141 v i = ev ss0 , in input port 10 20 100 k caution always use av dd pin with the same potential as the v dd pin. remark unless specified otherwise, the charac teristics of alternate-function pi ns are the same as those of the port pins. rl78/g1a 2. electrical specifications page 28 of 76 r01ds0151ej0001 rev.0.01 2011.12.26 under development preliminary document specifications in this document are tentative and subject to change. caution the pins mounted depend on the product. refer to 1.3.1 25-pin products to 1.3.4 64-pin products. 2.3.2 supply current characteristics (t a = ? 40 to +85 c, 1.6 v ev dd0 v dd 3.6 v, v ss = ev ss0 = 0 v) (1/2) parameter symbol conditions min. typ. max. unit basic operation v dd = 3.0 v 2.1 ma f ih = 32 mhz note 3 normal operation v dd = 3.0 v 4.6 7.0 ma f ih = 24 mhz note 3 normal operation v dd = 3.0 v 3.7 5.5 ma high-speed operation note 5 f ih = 16 mhz note 3 normal operation v dd = 3.0 v 2.7 4.0 ma v dd = 3.0 v 1.2 1.8 ma low-speed operation note 5 f ih = 8 mhz note 3 normal operation v dd = 2.0 v 1.2 1.8 ma v dd = 3.0 v 1.2 1.7 ma low-voltage operation note 5 f ih = 4 mhz note 3 normal operation v dd = 2.0 v 1.2 1.7 ma square wave input 3.0 4.6 ma f mx = 20 mhz note 2 , v dd = 3.0 v normal operation resonator connection 3.2 4.8 ma square wave input 1.9 2.7 ma high-speed operation note 5 f mx = 10 mhz note 2 , v dd = 3.0 v normal operation resonator connection 1.9 2.7 ma square wave input 1.1 1.7 ma f mx = 8 mhz note 2 , v dd = 3.0 v normal operation resonator connection 1.1 1.7 ma square wave input 1.1 1.7 ma low-speed operation note 5 f mx = 8 mhz note 2 , v dd = 2.0 v normal operation resonator connection 1.1 1.7 ma square wave input 4.1 a f sub = 32.768 khz note 4 t a = ? 40 c normal operation resonator connection 4.2 a square wave input 4.1 4.9 a f sub = 32.768 khz note 4 t a = +25 c normal operation resonator connection 4.2 5.0 a square wave input 4.2 5.5 a f sub = 32.768 khz note 4 t a = +50 c normal operation resonator connection 4.3 5.6 a square wave input 4.2 6.3 a f sub = 32.768 khz note 4 t a = +70 c normal operation resonator connection 4.3 6.4 a square wave input 4.8 7.7 a supply current i dd1 note 1 operating mode subsystem clock operation f sub = 32.768 khz note 4 t a = +85 c normal operation resonator connection 4.9 7.8 a ( notes and remarks are listed on the next page.) rl78/g1a 2. electrical specifications page 29 of 76 r01ds0151ej0001 rev.0.01 2011.12.26 under development preliminary document specifications in this document are tentative and subject to change. caution the pins mounted depend on the product. refer to 1.3.1 25-pin products to 1.3.4 64-pin products. notes 1. total current flowing into v dd and ev dd0 , including the input leakage current flowing when the level of the input pin is fixed to v dd , ev dd0 or v ss , ev ss0 . the values below the max. column include the peripheral operation current (except for background operation (bgo)). however, not including the current flowing into the a/d converter, lvd circ uit, i/o port, and on-chip pull-up/pull-down resistors. 2. when high-speed on-chip oscillator and subsystem clock are stopped. 3. when high-speed system clock and subsystem clock are stopped. 4. when high-speed on-chip oscillator and high-speed syst em clock are stopped. when real-time counter and watchdog timer is stopped. when amphs1 = 1 (ultra-low power consumption oscillation). 5. relationship between operation voltage width, oper ation frequency of cpu and operation mode is as below. high speed operation: v dd = 2.7 v to 3.6 v@1 mhz to 32 mhz, v dd = 2.4 v to 3.6 v@1 mhz to 16 mhz low speed operation: v dd = 1.8 v to 3.6 v@1 mhz to 8 mhz low voltage operation: v dd = 1.6 v to 3.6 v@1 mhz to 4 mhz remarks 1. f mx : high-speed system clock frequency (x1 clock oscillation frequency or external main system clock frequency) 2. f ih : high-speed on-chip oscillator clock frequency 3. f sub : subsystem clock frequency (xt1 clock oscillation frequency) 4. except subsystem clock operation, temper ature condition of t he typ. value is t a = 25 c rl78/g1a 2. electrical specifications page 30 of 76 r01ds0151ej0001 rev.0.01 2011.12.26 under development preliminary document specifications in this document are tentative and subject to change. caution the pins mounted depend on the product. refer to 1.3.1 25-pin products to 1.3.4 64-pin products. (t a = ? 40 to +85 c, 1.6 v ev dd0 v dd 3.6 v, v ss = ev ss0 = 0 v) (2/2) parameter symbol conditions min. typ. max. unit f ih = 32 mhz note 4 v dd = 3.0 v 0.54 1.63 ma f ih = 24 mhz note 4 v dd = 3.0 v 0.44 1.28 ma high-speed operation note 7 f ih = 16 mhz note 4 v dd = 3.0 v 0.40 1.00 ma v dd = 3.0 v 260 530 a low-speed operation note 7 f ih = 8 mhz note 4 v dd = 2.0 v 260 530 a v dd = 3.0 v 420 640 a low-voltage operation note 7 f ih = 4 mhz note 4 v dd = 2.0 v 420 640 a square wave input 0.28 1.00 ma f mx = 20 mhz note 3 , v dd = 3.0 v resonator connection 0.45 1.17 ma square wave input 0.19 0.60 ma high-speed operation note 7 f mx = 10 mhz note 3 , v dd = 3.0 v resonator connection 0.26 0.67 ma square wave input 95 330 a f mx = 8 mhz note 3 , v dd = 3.0 v resonator connection 145 380 a square wave input 95 330 a low-speed operation note 7 f mx = 8 mhz note 3 , v dd = 2.0 v resonator connection 145 380 a square wave input 0.25 a f sub = 32.768 khz note 5 t a = ? 40 c resonator connection 0.44 a square wave input 0.30 0.57 a f sub = 32.768 khz note 5 t a = +25 c resonator connection 0.49 0.76 a square wave input 0.33 1.17 a f sub = 32.768 khz note 5 t a = +50 c resonator connection 0.52 1.36 a square wave input 0.36 1.97 a f sub = 32.768 khz note 5 t a = +70 c resonator connection 0.55 2.16 a square wave input 0.97 3.37 a i dd2 note 2 halt mode subsystem clock operation f sub = 32.768 khz note 5 t a = +85 c resonator connection 1.16 3.56 a t a = ? 40 c 0.18 a t a = +25 c 0.23 0.50 a t a = +50 c 0.26 1.10 a t a = +70 c 0.29 1.90 a supply current note 1 i dd3 note 6 stop mode t a = +85 c 0.90 3.30 a ( notes and remarks are listed on the next page.) rl78/g1a 2. electrical specifications page 31 of 76 r01ds0151ej0001 rev.0.01 2011.12.26 under development preliminary document specifications in this document are tentative and subject to change. caution the pins mounted depend on the product. refer to 1.3.1 25-pin products to 1.3.4 64-pin products. notes 1. total current flowing into v dd and ev dd0 , including the input leakage current flowing when the level of the input pin is fixed to v dd , ev dd0 or v ss , ev ss0 . the values below the max. column include the peripheral operation current. however, not includin g the current flowing into the a/d converter, lvd circuit, i/o port, and on-chip pu ll-up/pull-down resistors. 2. during halt instruction execution by flash memory. 3. when high-speed on-chip oscillator and subsystem clock are stopped. 4. when high-speed system clock and subsystem clock are stopped. 5. when operating real-time clock (rtc) and setting ul tra-low current consumption (amphs1 = 1). when high-speed on-chip oscillator and high-speed system clock are stopped. when watchdog timer is stopped. the values below the max. column include the leakage current. 6. when high-speed on-chip oscillator, high-speed syst em clock, and subsystem clock are stopped. when watchdog timer is stopped. the values below the max. column include the leakage current. 7. relationship between operation voltage width, oper ation frequency of cpu and operation mode is as below. high speed operation: v dd = 2.7 v to 3.6 v@1 mhz to 32 mhz, v dd = 2.4 v to 3.6 v@1 mhz to 16 mhz low speed operation: v dd = 1.8 v to 3.6 v@1 mhz to 8 mhz low voltage operation: v dd = 1.6 v to 3.6 v@1 mhz to 4 mhz remarks 1. f mx : high-speed system clock frequency (x1 clock oscillation frequency or external main system clock frequency) 2. fih: high-speed on-chip oscillator clock frequency 3. fsub: subsystem clock frequency (xt1 clock oscillation frequency) 4. except subsystem clock operation and stop mode, temperature condition of the typ. value is t a = 25 c rl78/g1a 2. electrical specifications page 32 of 76 r01ds0151ej0001 rev.0.01 2011.12.26 under development preliminary document specifications in this document are tentative and subject to change. caution the pins mounted depend on the product. refer to 1.3.1 25-pin products to 1.3.4 64-pin products. (t a = ? 40 to +85 c, 1.6 v ev dd0 v dd 3.6 v, v ss = ev ss0 = 0 v) parameter symbol conditions min. typ. max. unit real-time clock operation 0.02 rtc operating current i rtc notes 1, 2 f sub = 32.768 khz interval timer operation 0.02 a watchdog timer operating current i wdt notes 2, 3 f il = 15 khz 0.22 a ani0 to ani12 460 1090 a reference power supply is other than the internal reference voltage, av dd = 3.6 v ani16 to ani30 400 950 a a/d converter operating current i adc note 4 reference power supply is the internal reference voltage, av dd = 3.6 v ani0 to ani12, ani16 to ani30 400 950 a temperature sensor operating current i tmps 75 a lvd operating current i lvi note 5 0.08 a bgo operating current i bgo note 6 2.50 12.20 ma notes 1. current flowing only to the real-time clock (excludin g the operating current of t he xt1 oscillator). the typ. value of the current value of the rl78/g1a is the sum of the typ. values of either i dd1 or i dd2 , and i rtc , when the real-time clock operates in operation mode or halt mode. the i dd1 and i dd2 max. values also include the real-time clock operating current. however, i dd2 subsystem clock operation includes the operational current of the real-time clock. 2. when high speed on-chip oscillator and high-speed system clock are stopped. 3. current flowing only to the watchdog timer (inclu ding the operating current of the low-speed on-chip oscillator). the current value of the rl78/g1a is the sum of i dd1 , i dd2 or i dd3 and i wdt when f clk = f sub when the watchdog timer operates in stop mode. 4. current flowing only to the a/d converter. the current value of the rl78/g1a is the sum of i dd1 or i dd2 and i adc when the a/d converter operates in an operation mode or the halt mode. 5. current flowing only to the lvd circuit. the current value of the rl78/g1a is the sum of i dd1 , i dd2 or i dd3 and i lvi when the lvd circuit operates in t he operating, halt or stop mode. 6. current flowing only to the bgo. the current value of the rl78/g1a is the sum of i dd1 or i dd2 and i bgo when the bgo operates in an operation mode. remarks 1. f il : low-speed on-chip oscillator clock frequency 2. f sub : subsystem clock frequency (xt1 clock oscillation frequency) 3. f clk : cpu/peripheral hardware clock frequency 4. temperature condition of the typ. value is t a = 25 c rl78/g1a 2. electrical specifications page 33 of 76 r01ds0151ej0001 rev.0.01 2011.12.26 under development preliminary document specifications in this document are tentative and subject to change. caution the pins mounted depend on the product. refer to 1.3.1 25-pin products to 1.3.4 64-pin products. 2.4 ac characteristics 2.4.1 basic operation (t a = ? 40 to +85 c, 1.6 v av dd 3.6 v, 1.6 v ev dd0 v dd 3.6 v, v ss = ev ss0 = 0 v) items symbol conditions min. typ. max. unit 2.7 v v dd 3.6 v 0.03125 1 s high-speed main mode 2.4 v v dd < 2.7 v 0.0625 1 s low voltage main mode 1.6 v v dd 3.6 v 0.25 1 s main system clock (f main ) operation low-speed main mode 1.8 v v dd 3.6 v 0.125 1 s subsystem clock (f sub ) operation 1.8 v v dd 3.6 v 28.5 30.5 31.3 s 2.7 v v dd 3.6 v 0.03125 1 s high-speed main mode 2.4 v v dd < 2.7 v 0.0625 1 s low voltage main mode 1.8 v v dd 3.6 v 0.25 1 s instruction cycle (minimum instruction execution time) t cy in the self programming mode low-speed main mode 1.8 v v dd 3.6 v 0.125 1 s 2.7 v v dd 3.6 v 1.0 20.0 mhz 1.8 v v dd < 2.7 v 1.0 8.0 mhz f ex 1.6 v v dd < 1.8 v 1.0 4.0 mhz external main system clock frequency f exs 32 35 khz 2.7 v v dd 3.6 v 24 ns 1.8 v v dd < 2.7 v 60 ns t exh , t exl 1.6 v v dd < 1.8 v 120 ns external main system clock input high-level width, low-level width t exhs , t exls 13.7 s ti00, ti01, ti03 to ti07 input high-level width, low-level width t tih , t til 1/f mck +10 ns note 2.7 v ev dd0 3.6 v 8 mhz 1.8 v ev dd0 < 2.7 v 4 mhz high-speed main mode 1.6 v ev dd0 < 1.8 v 2 mhz low voltage main mode 1.6 v ev dd0 3.6 v 2 mhz 1.8 v ev dd0 3.6 v 4 mhz to00, to01, to03 to to07 output frequency f to low-speed main mode 1.6 v ev dd0 < 1.8 v 2 mhz 2.7 v ev dd0 3.6 v 8 mhz 1.8 v ev dd0 < 2.7 v 4 mhz high-speed main mode 1.6 v ev dd0 < 1.8 v 2 mhz 1.8 v ev dd0 3.6 v 4 mhz low voltage main mode 1.6 v ev dd0 < 1.8 v 2 mhz 1.8 v ev dd0 3.6 v 4 mhz pclbuz0, pclbuz1 output frequency f pcl low-speed main mode 1.6 v ev dd0 < 1.8 v 2 mhz intp0 1.6 v v dd 3.6 v 1 s interrupt input high-level width, low-level width t inth , t intl intp1 to intp11 1.6 v ev dd0 3.6 v 1 s 1.8 v ev dd0 3.6 v, 1.8 v av dd 3.6 v 250 ns key interrupt input low-level width t kr kr0 to kr9 1.6 v ev dd0 < 1.8 v, 1.6 v av dd < 1.8 v 1 s reset low-level width t rsl 10 s ( note, caution and remark are listed on the next page.) rl78/g1a 2. electrical specifications page 34 of 76 r01ds0151ej0001 rev.0.01 2011.12.26 under development preliminary document specifications in this document are tentative and subject to change. caution the pins mounted depend on the product. refer to 1.3.1 25-pin products to 1.3.4 64-pin products. note the following conditions are required for low voltage interface when e vdd0 rl78/g1a 2. electrical specifications page 36 of 76 r01ds0151ej0001 rev.0.01 2011.12.26 under development preliminary document specifications in this document are tentative and subject to change. caution the pins mounted depend on the product. refer to 1.3.1 25-pin products to 1.3.4 64-pin products. (2) during communication at same poten tial (csi mode) (master mode (f mck /2), sckp... internal clock output) (t a = ? 40 to +85 c, 2.7 v ev dd0 v dd 3.6 v, v ss = ev ss0 = 0 v) parameter symbol conditions min. typ. max. unit sckp cycle time t kcy1 2.7 v ev dd0 3.6 v 83.3 note 1 ns sckp high-/low-level width t kh1 , t kl1 2.7 v ev dd0 3.6 v t kcy1 /2 ? 10 ns sip setup time (to sckp ) note 2 t sik1 2.7 v ev dd0 3.6 v 33 note 5 ns sip hold time (from sckp ) note 3 t ksi1 2.7 v ev dd0 3.6 v 10 ns delay time from sckp to sop output note 4 t kso1 c = 20 pf note 6 10 ns notes 1. the value must also be 2/f clk or more. 2. when dapmn = 0 and ckpmn = 0, or dapmn = 1 and ckpmn = 1. the sip setup time becomes ?to sckp ? when dapmn = 0 and ckpmn = 1, or dapmn = 1 and ckpmn = 0. 3. when dapmn = 0 and ckpmn = 0, or dapmn = 1 and ckpmn = 1. the sip hold time becomes ?from sckp ? when dapmn = 0 and ckpmn = 1, or dapmn = 1 and ckpmn = 0. 4. when dapmn = 0 and ckpmn = 0, or dapmn = 1 and ckpmn = 1. the delay time to sop output becomes ?from sckp ? when dapmn = 0 and ckpmn = 1, or dapmn = 1 and ckpmn = 0. 5. using the f mck within 24 mhz. 6. c is the load capacitance of the sckp and sop output lines. caution select the normal input buffer for the sip pin and the normal output mode for the sop pin and sckp pin by using port input mode register g (pimg) and port ou tput mode register g (pomg). remarks 1. this specification is valid only when csi00?s peripheral i/o r edirect function is not used. 2. p: csi number (p = 00), m: unit number (m = 0), n: channel number (n = 0), g: pim and pom numbers (g = 1) 3. f mck : serial array unit operation clock frequency (operation clock to be set by the cksmn bit of serial mode register mn (smrmn). m: unit number, n: channel number (mn = 00)) rl78/g1a 2. electrical specifications page 37 of 76 r01ds0151ej0001 rev.0.01 2011.12.26 under development preliminary document specifications in this document are tentative and subject to change. caution the pins mounted depend on the product. refer to 1.3.1 25-pin products to 1.3.4 64-pin products. (3) during communication at same poten tial (csi mode) (master mode (f mck /4), sckp... internal clock output) (t a = ? 40 to +85 c, 1.6 v ev dd0 v dd 3.6 v, v ss = ev ss0 = 0 v) notes 1. the value must also be 4/f clk or more. 2. when dapmn = 0 and ckpmn = 0, or dapmn = 1 and c kpmn = 1. the sip setup time becomes ?to sckp ? when dapmn = 0 and ckpmn = 1, or dapmn = 1 and ckpmn = 0. 3. when dapmn = 0 and ckpmn = 0, or dapmn = 1 and ckpmn = 1. the sip hold time becomes ?from sckp ? when dapmn = 0 and ckpmn = 1, or dapmn = 1 and ckpmn = 0. 4. when dapmn = 0 and ckpmn = 0, or dapmn = 1 and ckpmn = 1. the delay time to sop output becomes ?from sckp ? when dapmn = 0 and ckpmn = 1, or dapmn = 1 and ckpmn = 0. 5. c is the load capacitance of the sckp and sop output lines. caution select the normal input buffer for the sip pin and the normal output mode for the sop pin and sckp pin by using port input mode register g (pimg) and port ou tput mode register g (pomg). remarks 1. this specification is valid on ly when csi00?s peripheral i/o redi rect function is not used. 2. p: csi number (p = 00, 01, 10, 11, 20, 21), m: unit number (m = 0, 1), n: channel number (n = 0 to 2), g: pim and pom numbers (g = 0, 1) 3. f mck : serial array unit operation clock frequency (operation clock to be set by the cksmn bit of serial mode register mn (smrmn). m: unit number, n: channel number (mn = 00 to 03, 10, 11)) parameter symbol conditions min. typ. max. unit 2.7 v ev dd0 3.6 v 125 note 1 ns 2.4 v ev dd0 3.6 v 250 note 1 ns 1.8 v ev dd0 3.6 v 500 note 1 ns sckp cycle time t kcy1 1.6 v ev dd0 3.6 v 1000 note 1 ns 2.7 v ev dd0 3.6 v t kcy1 /2 ? 18 ns 2.4 v ev dd0 3.6 v t kcy1 /2 ? 38 ns 1.8 v ev dd0 3.6 v t kcy1 /2 ? 50 ns sckp high-/low-level width t kh1 , t kl1 1.6 v ev dd0 3.6 v t kcy1 /2 ? 100 ns 2.7 v ev dd0 3.6 v 38 ns 2.4 v ev dd0 3.6 v 75 ns 1.8 v ev dd0 3.6 v 150 ns sip setup time (to sckp ) note 2 t sik1 1.6 v ev dd0 3.6 v 300 ns sip hold time (from sckp ) note 3 t ksi1 19 ns delay time from sckp to sop output note 4 t kso1 c = 30 pf note 5 25 ns rl78/g1a 2. electrical specifications page 38 of 76 r01ds0151ej0001 rev.0.01 2011.12.26 under development preliminary document specifications in this document are tentative and subject to change. caution the pins mounted depend on the product. refer to 1.3.1 25-pin products to 1.3.4 64-pin products. (4) during communication at same potential (csi mode) (slave m ode, sckp... external clock input) (t a = ? 40 to +85 c, 1.6 v ev dd0 v dd 3.6 v, v ss = ev ss0 = 0 v) parameter symbol conditions min. typ. max. unit 16 mhz < f mck 8/f mck ns 2.7 v ev dd0 < 3.6 v f mck 16 mhz 6/f mck ns 16 mhz < f mck 8/f mck ns 1.8 v ev dd0 < 2.7 v f mck 16 mhz 6/f mck ns sckp cycle time note 5 t kcy2 1.6 v ev dd0 < 1.8 v 6/f mck ns sckp high-/low-level width t kh2 , t kl2 1.6 v ev dd0 3.6 v t kcy2 /2 ns 2.7 v ev dd0 3.6 v 50 ns 1.8 v ev dd0 < 2.7 v 80 ns sip setup time (to sckp ) note 1 t sik2 1.6 v ev dd0 < 1.8 v 160 ns 2.7 v ev dd0 3.6 v 1/f mck +31 ns 1.8 v ev dd0 < 2.7 v 1/f mck +31 ns sip hold time (from sckp ) note 2 t ksi2 1.6 v ev dd0 < 1.8 v 1/f mck + 250 ns 2.7 v ev dd0 < 3.6 v 2/f mck +44 ns 2.4 v ev dd0 < 2.7 v 2/f mck +75 ns 1.8 v ev dd0 < 2.4 v 2/f mck +110 ns delay time from sckp to sop output note 3 t kso2 c = 30 pf note 4 1.6 v ev dd0 < 1.8 v 2/f mck +220 ns notes 1. when dapmn = 0 and ckpmn = 0, or dapmn = 1 a nd ckpmn = 1. the sip setup time becomes ?to sckp ? when dapmn = 0 and ckpmn = 1, or dapmn = 1 and ckpmn = 0. 2. when dapmn = 0 and ckpmn = 0, or dapmn = 1 and ckpmn = 1. the sip hold time becomes ?from sckp ? when dapmn = 0 and ckpmn = 1, or dapmn = 1 and ckpmn = 0. 3. when dapmn = 0 and ckpmn = 0, or dapmn = 1 and ckpmn = 1. the delay time to sop output becomes ?from sckp ? when dapmn = 0 and ckpmn = 1, or dapmn = 1 and ckpmn = 0. 4. c is the load capacitance of the sop output lines. 5. transfer rate in the snooze mode : max. 1 mbps caution select the ttl input buffer for the sip pin a nd sckp pin and the normal output mode for the sop pin by using port input mode register g (p img) and port output mode register g (pomg). remarks 1. p: csi number (p = 00, 01, 10, 11, 20, 21), m: unit number (m = 0, 1), n: channel number (n = 0 to 2), g: pim number (g = 0, 1) 2. f mck : serial array unit operation clock frequency (operation clock to be set by the cksmn bit of se rial mode register mn (smrmn). m: unit number, n: channel number (mn = 00 to 03, 10, 11)) rl78/g1a 2. electrical specifications page 39 of 76 r01ds0151ej0001 rev.0.01 2011.12.26 under development preliminary document specifications in this document are tentative and subject to change. caution the pins mounted depend on the product. refer to 1.3.1 25-pin products to 1.3.4 64-pin products. csi mode connection diagram (duri ng communication at same potential) user's device sckp sop sck si sip so rl78/g1a csi mode serial transfer timing (during communication at same potential) (when dapmn = 0 and ckpmn = 0, or dapmn = 1 and ckpmn = 1.) sip input data output data sop t kcy1, 2 t kl1, 2 t kh1, 2 t sik1, 2 t ksi1, 2 t kso1, 2 sckp csi mode serial transfer timing (during communication at same potential) (when dapmn = 0 and ckpmn = 1, or dapmn = 1 and ckpmn = 0.) sip input data output data sop t kcy1, 2 t kh1, 2 t kl1, 2 t sik1, 2 t ksi1, 2 t kso1, 2 sckp remarks 1. p: csi number (p = 00, 01, 10, 11, 20, 21) 2. m: unit number, n: channel nu mber (mn = 00 to 03, 10, 11) rl78/g1a 2. electrical specifications page 40 of 76 r01ds0151ej0001 rev.0.01 2011.12.26 under development preliminary document specifications in this document are tentative and subject to change. caution the pins mounted depend on the product. refer to 1.3.1 25-pin products to 1.3.4 64-pin products. (5) during communication at sam e potential (simplified i 2 c mode) (t a = ? 40 to +85 c, 1.6 v ev dd0 v dd 3.6 v, v ss = ev ss0 = 0 v) parameter symbol conditions min. max. unit 2.7 v ev dd0 3.6 v, c b = 50 pf, r b = 2.7 k 1000 khz 1.8 v ev dd0 3.6 v, c b = 100 pf, r b = 3 k 400 khz 1.8 v ev dd0 < 2.7 v, c b = 100 pf, r b = 5 k 300 khz sclr clock frequency f scl 1.6 v ev dd0 < 1.8 v, c b = 100 pf, r b = 5 k 250 khz 2.7 v ev dd0 3.6 v, c b = 50 pf, r b = 2.7 k 475 ns 1.8 v ev dd0 3.6 v, c b = 100 pf, r b = 3 k 1150 ns 1.8 v ev dd0 < 2.7 v, c b = 100 pf, r b = 5 k 1550 ns hold time when sclr = ?l? t low 1.6 v ev dd0 < 1.8 v, c b = 100 pf, r b = 5 k 1850 ns 2.7 v ev dd0 3.6 v, c b = 50 pf, r b = 2.7 k 475 ns 1.8 v ev dd0 3.6 v, c b = 100 pf, r b = 3 k 1150 ns 1.8 v ev dd0 < 2.7 v, c b = 100 pf, r b = 5 k 1550 ns hold time when sclr = ?h? t high 1.6 v ev dd0 < 1.8 v, c b = 100 pf, r b = 5 k 1850 ns 2.7 v ev dd0 3.6 v, c b = 50 pf, r b = 2.7 k 1/f mck + 85 note ns 1.8 v ev dd 3.6 v, c b = 100 pf, r b = 3 k 1/f mck + 145 note ns 1.8 v ev dd0 < 2.7 v, c b = 100 pf, r b = 5 k 1/f mck + 230 note ns data setup time (reception) t su:dat 1.6 v ev dd0 < 1.8 v, c b = 100 pf, r b = 5 k 1/f mck + 290 note ns 2.7 v ev dd0 3.6 v, c b = 50 pf, r b = 2.7 k 0 305 ns 1.8 v ev dd0 3.6 v, c b = 100 pf, r b = 3 k 0 355 ns 1.8 v ev dd0 < 2.7 v, c b = 100 pf, r b = 5 k 0 405 ns data hold time (transmission) t hd:dat 1.6 v ev dd0 < 1.8 v, c b = 100 pf, r b = 5 k 0 405 ns note set the f mck value to keep the hold time of sclr = "l" and sclr = "h". ( caution and remarks are listed on the next page.) rl78/g1a 2. electrical specifications page 41 of 76 r01ds0151ej0001 rev.0.01 2011.12.26 under development preliminary document specifications in this document are tentative and subject to change. caution the pins mounted depend on the product. refer to 1.3.1 25-pin products to 1.3.4 64-pin products. simplified i 2 c mode mode connection diagram (dur ing communication at same potential) user's device sdar sclr sda scl v dd r b rl78/g1a simplified i 2 c mode serial transfer timing (dur ing communication at same potential) sdar t low t high t hd:dat sclr t su:dat 1/f scl caution select the ttl input buffer and the n-ch open drain output (v dd tolerance) mode for the sdar pin and the normal output mode for the sclr pin by us ing port input mode register g (pimg) and port output mode register h (pomh). remarks 1. r b [ ]:communication line (sdar) pull-up resistance, c b [f]: communication line (sdar, sclr) load capacitance 2. r: iic number (r = 00, 01, 10, 11, 20, 21), g: pim number (g = 0, 1), h: pom number (h = 0, 1) 3. f mck : serial array unit operation clock frequency (operation clock to be set by the cksmn bit of seri al mode register mn (smrmn). m: unit number (m = 0, 1), n: channel number (n = 0 to 3), mn = 00 to 03, 10, 11) rl78/g1a 2. electrical specifications page 42 of 76 r01ds0151ej0001 rev.0.01 2011.12.26 under development preliminary document specifications in this document are tentative and subject to change. caution the pins mounted depend on the product. refer to 1.3.1 25-pin products to 1.3.4 64-pin products. (6) communication at different potential (2.5 v) (uart mode) (dedicat ed baud rate generator output) (1/2) (t a = ? 40 to +85 c, 1.8 v ev dd0 v dd 3.6 v, v ss = ev ss0 = 0 v) parameter symbol conditions min. typ. max. unit f mck /6 note 1 bps 2.7 v ev dd0 < 3.6 v, 2.3 v v b 2.7 v theoretical value of the maximum transfer rate f clk = 32 mhz, f mck = f clk 5.3 mbps f mck /6 notes 1 to 3 bps transfer rate reception 1.8 v ev dd0 < 3.3 v, 1.6 v v b 2.0 v theoretical value of the maximum transfer rate f clk = 8 mhz, f mck = f clk 1.3 mbps notes 1. transfer rate in the snooze m ode : max. 9600 bps, min. 4800 bps 2. use it with ev dd0 v b . 3. the following conditions are required for low voltage interface when ev dd0 < v dd . 2.4 v ev dd0 < 2.7 v : max. 2.6 mbps 1.8 v ev dd0 < 2.4 v : max. 1.3 mbps 1.6 v ev dd0 < 1.8 v : max. 0.6 mbps caution select the ttl input buffer for the rxdq pin and the n-ch open drain output (v dd tolerance) mode for the txdq pin by using port input mode regist er g (pimg) and port output mode register g (pomg). remarks 1. v b [v]: communication line voltage 2. q: uart number (q = 0 to 2), g: pim and pom number (g = 0, 1) 3. f mck : serial array unit operation clock frequency (operation clock to be set by the cksmn bit of seri al mode register mn (smrmn). m: unit number, n: channel number (mn = 00 to 03, 10, 11) 4. v ih and v il below are observation points for the ac c haracteristics of the serial array unit when communicating at different potentials in uart mode. 2.7 v ev dd0 < 3.6 v, 2.3 v v b 2.7 v: v ih = 2.0 v, v il = 0.5 v 1.8 v ev dd0 < 3.3 v, 1.6 v v b 2.0 v: v ih = 1.5 v, v il = 0.32 v 5. uart2 cannnot communicate at di fferent potential when bit 1 (pior 1) of peripheral i/o redirection register (pior) is 1. rl78/g1a 2. electrical specifications page 43 of 76 r01ds0151ej0001 rev.0.01 2011.12.26 under development preliminary document specifications in this document are tentative and subject to change. caution the pins mounted depend on the product. refer to 1.3.1 25-pin products to 1.3.4 64-pin products. (6) communication at different potential (2.5 v) (uart mode) (dedicat ed baud rate generator output) (2/2) (t a = ? 40 to +85 c, 1.8 v ev dd0 v dd 3.6 v, v ss = ev ss0 = 0 v) parameter symbol conditions min. typ. max. unit notes 1, 2 bps 2.7 v ev dd0 < 3.6 v, 2.3 v v b 2.7 v theoretical value of the maximum transfer rate c b = 50 pf, r b = 2.7 k , v b = 2.3 v 1.2 note 5 mbps notes 1, 4, 5 bps transfer rate transmission 1.8 v ev dd0 < 3.3 v, 1.6 v v b 2.0 v theoretical value of the maximum transfer rate c b = 50 pf, r b = 5.5 k , v b = 1.6 v 0.43 note 6 mbps notes 1. transfer rate in the snooze m ode : max. 9600 bps, min. 4800 bps 2. the smaller maximum transfer rate derived by using f mck /6 or the following expression is the valid maximum transfer rate. expression for calculating the transfer rate when 2.7 v ev dd0 < 3.6 v and 2.3 v v b 2.7 v 1 maximum transfer rate = { ? c b r b ln (1 ? 2.0 v b )} 3 [bps] 1 transfer rate 2 ? { ? c b r b ln (1 ? 2.0 v b )} baud rate error (theoretical value) = 100 [%] ( 1 transfer rate ) number of transferred bits * this value is the theoretical value of the relati ve difference between the transmission and reception sides. 3. this value as an example is calculated when the c onditions described in the ?conditions? column are met. refer to note 2 above to calculate the maxi mum transfer rate under conditions of the customer. 4. use it with ev dd0 v b . 5. the smaller maximum transfer rate derived by using f mck /6 or the following expression is the valid maximum transfer rate. expression for calculating the transfer rate when 1.8 v ev dd0 < 3.3 v and 1.6 v v b 2.0 v 1 maximum transfer rate = [bps] { ? c b r b ln (1 ? 1.5 v b )} 3 1 transfer rate 2 ? { ? c b r b ln (1 ? 1.5 v b )} baud rate error (theoretical value) = 100 [%] ( 1 transfer rate ) number of transferred bits * this value is the theoretical value of the relati ve difference between the transmission and reception sides. 6. this value as an example is calculated when the c onditions described in the ?conditions? column are met. refer to note 7 above to calculate the maxi mum transfer rate under conditions of the customer. rl78/g1a 2. electrical specifications page 44 of 76 r01ds0151ej0001 rev.0.01 2011.12.26 under development preliminary document specifications in this document are tentative and subject to change. caution the pins mounted depend on the product. refer to 1.3.1 25-pin products to 1.3.4 64-pin products. caution select the ttl input buffer for the rxdq pin and the n-ch open drain output (v dd tolerance) mode for the txdq pin by using port input mode regi ster g (pimg) and port output mode register g (pomg). remarks 1. r b [ ]:communication line (txdq) pull-up resistance, c b [f]: communication line (txdq) load capacitance, v b [v]: communication line voltage 2. q: uart number (q = 0 to 2), g: pim and pom number (g = 0, 1) 3. f mck : serial array unit operation clock frequency (operation clock to be set by the cksmn bit of serial mode register mn (smrmn). m: unit number, n: channel nu mber (mn = 00 to 03, 10, 11)) 4. v ih and v il below are observation points for the ac char acteristics of the serial array unit when communicating at different potentials in uart mode. 2.7 v ev dd0 < 3.6 v, 2.3 v v b 2.7 v: v ih = 2.0 v, v il = 0.5 v 1.8 v ev dd0 < 3.3 v, 1.6 v v b 2.0 v: v ih = 1.5 v, v il = 0.32 v 5. uart2 cannot communicate at different potential when bit 1 (pior1) of peripheral i/o redirection register (pior) is 1. uart mode connection diagram (during communication at different potential) user's device txdq rxdq rx tx v b r b rl78/g1a rl78/g1a 2. electrical specifications page 45 of 76 r01ds0151ej0001 rev.0.01 2011.12.26 under development preliminary document specifications in this document are tentative and subject to change. caution the pins mounted depend on the product. refer to 1.3.1 25-pin products to 1.3.4 64-pin products. uart mode bit width (during communication at different potential) (reference) txdq rxdq baud rate error tolerance baud rate error tolerance low-bit width high-/low-bit width high-bit width 1/transfer rate 1/transfer rate caution select the ttl input buffer for the rxdq pin and the n-ch open drain output (v dd tolerance) mode for the txdq pin by using port input mode regist er g (pimg) and port output mode register g (pomg). remarks 1. uart2 cannot communicate at different potentia when bit 1 (pior1) of peripheral i/o redirection register (pior) is 1. 2. r b [ ]:communication line (txdq) pull-up resistance, v b [v]: communication line voltage 3. q: uart number (q = 0 to 2), g: pim and pom number (g = 0, 1) rl78/g1a 2. electrical specifications page 46 of 76 r01ds0151ej0001 rev.0.01 2011.12.26 under development preliminary document specifications in this document are tentative and subject to change. caution the pins mounted depend on the product. refer to 1.3.1 25-pin products to 1.3.4 64-pin products. (7) communication at different potential (2.5 v) (f mck /2) (csi mode) (master mode, sckp... internal clock output) (t a = ? 40 to +85 c, 2.7 v ev dd0 v dd 3.6 v, v ss = ev ss0 = 0 v) parameter symbol conditions min. typ. max. unit sckp cycle time t kcy1 2.7 v ev dd0 < 3.6 v, 2.3 v v b 2.7 v, c b = 20 pf, r b = 2.7 k 300 note 1 ns sckp high-level width t kh1 2.7 v ev dd0 < 3.6 v, 2.3 v v b 2.7 v, c b = 20 pf, r b = 2.7 k t kcy1 /2 ? 120 ns sckp low-level width t kl1 2.7 v ev dd0 < 3.6 v, 2.3 v v b 2.7 v, c b = 20 pf, r b = 2.7 k t kcy1 /2 ? 10 ns sip setup time (to sckp ) note 2 t sik1 2.7 v ev dd0 < 3.6 v, 2.3 v v b 2.7 v, c b = 20 pf, r b = 2.7 k 121 ns sip hold time (from sckp ) note 2 t ksi1 2.7 v ev dd0 < 3.6 v, 2.3 v v b 2.7 v, c b = 20 pf, r b = 2.7 k 10 ns delay time from sckp to sop output note 2 t kso1 2.7 v ev dd0 < 3.6 v, 2.3 v v b 2.7 v, c b = 20 pf, r b = 2.7 k 130 ns sip setup time (to sckp ) note 3 t sik1 2.7 v ev dd0 < 3.6 v, 2.3 v v b 2.7 v, c b = 20 pf, r b = 2.7 k 33 ns sip hold time (from sckp ) note 3 t ksi1 2.7 v ev dd0 < 3.6 v, 2.3 v v b 2.7 v, c b = 20 pf, r b = 2.7 k 10 ns delay time from sckp to sop output note 3 t kso1 2.7 v ev dd0 < 3.6 v, 2.3 v v b 2.7 v, c b = 20 pf, r b = 2.7 k 10 ns notes 1. the value must also be 2/f clk or more. 2. when dapmn = 0 and ckpmn = 0, or dapmn = 1 and ckpmn = 1. 3. when dapmn = 0 and ckpmn = 1, or dapmn = 1 and ckpmn = 0. ( caution and remark are listed on the next page.) rl78/g1a 2. electrical specifications page 47 of 76 r01ds0151ej0001 rev.0.01 2011.12.26 under development preliminary document specifications in this document are tentative and subject to change. caution the pins mounted depend on the product. refer to 1.3.1 25-pin products to 1.3.4 64-pin products. csi mode connection diagram (during communication at different potential) v b r b user's device rl78/g1a 2. electrical specifications page 48 of 76 r01ds0151ej0001 rev.0.01 2011.12.26 under development preliminary document specifications in this document are tentative and subject to change. caution the pins mounted depend on the product. refer to 1.3.1 25-pin products to 1.3.4 64-pin products. (8) communication at different potential (2.5 v) (f mck /4) (csi mode) (master mode, sckp... internal clock output) (1/2) (t a = ? 40 to +85 c, 1.8 v ev dd0 v dd 3.6 v, v ss = ev ss0 = 0 v) parameter symbol conditions min. typ. max. unit 2.7 v ev dd0 < 3.6 v, 2.3 v v b 2.7 v, c b = 30 pf, r b = 2.7 k 500 note ns sckp cycle time t kcy1 1.8 v ev dd0 < 3.3 v, 1.6 v v b 2.0 v, c b = 30 pf, r b = 5.5 k 1150 note ns 2.7 v ev dd0 < 3.6 v, 2.3 v v b 2.7 v, c b = 30 pf, r b = 2.7 k t kcy1 /2 ? 170 ns sckp high-level width t kh1 1.8 v ev dd0 < 3.3 v, 1.6 v v b 2.0 v, c b = 30 pf, r b = 5.5 k t kcy1 /2 ? 458 ns 2.7 v ev dd0 < 3.6 v, 2.3 v v b 2.7 v, c b = 30 pf, r b = 2.7 k t kcy1 /2 ? 18 ns sckp low-level width t kl1 1.8 v ev dd0 < 3.3 v, 1.6 v v b 2.0 v, c b = 30 pf, r b = 5.5 k t kcy1 /2 ? 50 ns note the value must also be 4/f clk or more. cautions 1. select the ttl input buffer for the sip pin and the n-ch open drain output (v dd tolerance) mode for the sop pin and sckp pin by using po rt input mode register g (pimg) and port output mode register g (pomg). 2. use it with ev dd0 v b . remarks 1. r b [ ]:communication line (sckp, sop) pull-up resistance, c b [f]: communication line (sckp, sop) load capacitance, v b [v]: communication line voltage 2. p: csi number (p = 00, 01, 10, 20), m: unit num ber , n: channel number (mn = 00, 01, 02, 10), g: pim and pom number (g = 0, 1) 3. v ih and v il below are observation points for the ac char acteristics of the serial array unit when communicating at different potentials in csi mode. 2.7 v ev dd0 < 3.6 v, 2.3 v v b 2.7 v: v ih = 2.0 v, v il = 0.5 v 1.8 v ev dd0 < 3.3 v, 1.6 v v b 2.0 v: v ih = 1.5 v, v il = 0.32 v 4. csi01, csi11 and csi21 cannot communicate at di fferent potential. use other csi for communication at different potential. rl78/g1a 2. electrical specifications page 49 of 76 r01ds0151ej0001 rev.0.01 2011.12.26 under development preliminary document specifications in this document are tentative and subject to change. caution the pins mounted depend on the product. refer to 1.3.1 25-pin products to 1.3.4 64-pin products. (8) communication at different potential (2.5 v) (f mck /4) (csi mode) (master mode, sckp... internal clock output) (2/2) (t a = ? 40 to +85 c, 1.8 v ev dd0 v dd 3.6 v, v ss = ev ss0 = 0 v) parameter symbol conditions min. typ. max. unit 2.7 v ev dd0 < 3.6 v, 2.3 v v b 2.7 v, c b = 30 pf, r b = 2.7 k 177 ns sip setup time (to sckp ) note 1 t sik1 1.8 v ev dd0 < 3.3 v, 1.6 v v b 2.0 v, c b = 30 pf, r b = 5.5 k 479 ns 2.7 v ev dd0 < 3.6 v, 2.3 v v b 2.7 v, c b = 30 pf, r b = 2.7 k 19 ns sip hold time (from sckp ) note 1 t ksi1 1.8 v ev dd0 < 3.3 v, 1.6 v v b 2.0 v, c b = 30 pf, r b = 5.5 k 19 ns 2.7 v ev dd0 < 3.6 v, 2.3 v v b 2.7 v, c b = 30 pf, r b = 2.7 k 195 ns delay time from sckp to sop output note 1 t kso1 1.8 v ev dd0 < 3.3 v, 1.6 v v b 2.0 v, c b = 30 pf, r b = 5.5 k 483 ns 2.7 v ev dd0 < 3.6 v, 2.3 v v b 2.7 v, c b = 30 pf, r b = 2.7 k 44 ns sip setup time (to sckp ) note 2 t sik1 1.8 v ev dd0 < 3.3 v, 1.6 v v b 2.0 v, c b = 30 pf, r b = 5.5 k 110 ns 2.7 v ev dd0 < 3.6 v, 2.3 v v b 2.7 v, c b = 30 pf, r b = 2.7 k 19 ns sip hold time (from sckp ) note 2 t ksi1 1.8 v ev dd0 < 3.3 v, 1.6 v v b 2.0 v, c b = 30 pf, r b = 5.5 k 19 ns 2.7 v ev dd0 < 3.6 v, 2.3 v v b 2.7 v, c b = 30 pf, r b = 2.7 k 25 ns delay time from sckp to sop output note 2 t kso1 1.8 v ev dd0 < 3.3 v, 1.6 v v b 2.0 v, c b = 30 pf, r b = 5.5 k 25 ns notes 1. when dapmn = 0 and ckpmn = 0, or dapmn = 1 and ckpmn = 1. 2. when dapmn = 0 and ckpmn = 1, or dapmn = 1 and ckpmn = 0. ( cautions and remarks are listed on the next page.) rl78/g1a 2. electrical specifications page 50 of 76 r01ds0151ej0001 rev.0.01 2011.12.26 under development preliminary document specifications in this document are tentative and subject to change. caution the pins mounted depend on the product. refer to 1.3.1 25-pin products to 1.3.4 64-pin products. csi mode connection diagram (during communication at different potential) v b r b user's device rl78/g1a 2. electrical specifications page 51 of 76 r01ds0151ej0001 rev.0.01 2011.12.26 under development preliminary document specifications in this document are tentative and subject to change. caution the pins mounted depend on the product. refer to 1.3.1 25-pin products to 1.3.4 64-pin products. csi mode serial transfer timing (master mode) (during communication at different potential) (when dapmn = 0 and ckpmn = 0, or dapmn = 1 and ckpmn = 1.) sip input data output data sop t kcy1 t kl1 t kh1 t sik1 t ksi1 t kso1 sckp csi mode serial transfer timing (master mode) (during communication at different potential) (when dapmn = 0 and ckpmn = 1, or dapmn = 1 and ckpmn = 0.) sip input data output data sop t kcy1 t kl1 t kh1 t sik1 t ksi1 t kso1 sckp caution select the ttl input buffer for the sip pin and the n-ch open drain output (v dd tolerance) mode for the sop pin and sckp pin by using port input mode register g (pimg) and port output mode register g (pomg). remarks 1. p: csi number (p = 00, 01, 10, 20), m: unit number, n: channel number (m = 00, 01, 02, 10), g: pim and pom number (g = 0, 1) 2. csi01, csi11 and csi21 cannot communicate at di fferent potential. use other csi for communication at different potential. rl78/g1a 2. electrical specifications page 52 of 76 r01ds0151ej0001 rev.0.01 2011.12.26 under development preliminary document specifications in this document are tentative and subject to change. caution the pins mounted depend on the product. refer to 1.3.1 25-pin products to 1.3.4 64-pin products. (9) communication at different potential (2.5 v) (csi mode) (slave mode, s ckp... external clock input) (t a = ? 40 to +85 c, 1.8 v ev dd0 v dd 3.6 v, v ss = ev ss0 = 0 v) parameter symbol conditions min. typ. max. unit 24 mhz < f mck 20/f mck ns 20 mhz < f mck 24 mhz 16/f mck ns 16 mhz < f mck 20 mhz 14/f mck ns 8 mhz < f mck 16 mhz 12/f mck ns 4 mhz < f mck 8 mhz 8/f mck ns 2.7 v ev dd0 < 3.6 v, 2.3 v v b 2.7 v f mck 4 mhz 6/f mck ns 24 mhz < f mck 48/f mck ns 20 mhz < f mck 24 mhz 36/f mck ns 16 mhz < f mck 20 mhz 32/f mck ns 8 mhz < f mck 16 mhz 26/f mck ns 4 mhz < f mck 8 mhz 16/f mck ns sckp cycle time note 1 t kcy2 1.8 v ev dd0 < 3.3 v, 1.6 v v b 2.0 v note 2 f mck 4 mhz 10/f mck ns 2.7 v ev dd0 < 3.6 v, 2.3 v v b 2.7 v t kcy2 /2 ? 18 ns sckp high-/low-level width t kh2 , t kl2 1.8 v ev dd0 < 3.3 v, 1.6 v v b 2.0 v note 2 t kcy2 /2 ? 50 ns 2.7 v ev dd0 3.6 v 60 ns sip setup time (to sckp ) note 3 t sik2 1.8 v ev dd0 < 3.3 v 97 ns sip hold time (from sckp ) note 4 t ksi2 1/f mck + 31 ns 2.7 v ev dd0 < 3.6 v, 2.3 v v b 2.7 v, c b = 30 pf, r b = 2.7 k 2/f mck + 214 ns delay time from sckp to sop output note 5 t kso2 1.8 v ev dd0 < 3.3 v, 1.6 v v b 2.0 v note 2 , c b = 30 pf, r b = 5.5 k 2/f mck + 573 ns notes 1. transfer rate in the snooze mode : max. 1 mbps 2. use it with ev dd0 v b . 3. when dapmn = 0 and ckpmn = 0, or dapmn = 1 and ckpmn = 1. the sip setup time becomes ?to sckp ? when dapmn = 0 and ckpmn = 1, or dapmn = 1 and ckpmn = 0. 4. when dapmn = 0 and ckpmn = 0, or dapmn = 1 and ckpmn = 1. the sip hold time becomes ?from sckp ? when dapmn = 0 and ckpmn = 1, or dapmn = 1 and ckpmn = 0. 5. when dapmn = 0 and ckpmn = 0, or dapmn = 1 and ckpmn = 1. the delay time to sop output becomes ?from sckp ? when dapmn = 0 and ckpmn = 1, or dapmn = 1 and ckpmn = 0. ( caution and remarks are listed on the next page.) rl78/g1a 2. electrical specifications page 53 of 76 r01ds0151ej0001 rev.0.01 2011.12.26 under development preliminary document specifications in this document are tentative and subject to change. caution the pins mounted depend on the product. refer to 1.3.1 25-pin products to 1.3.4 64-pin products. csi mode connection diagram (during communication at different potential) user's device rl78/g1a 2. electrical specifications page 54 of 76 r01ds0151ej0001 rev.0.01 2011.12.26 under development preliminary document specifications in this document are tentative and subject to change. caution the pins mounted depend on the product. refer to 1.3.1 25-pin products to 1.3.4 64-pin products. csi mode serial transfer timi ng (slave mode) (during communication at different potential) (when dapmn = 0 and ckpmn = 0, or dapmn = 1 and ckpmn = 1.) sip input data output data sop t kcy2 t kl2 t kh2 t sik2 t ksi2 t kso2 sckp csi mode serial transfer timi ng (slave mode) (during communication at different potential) (when dapmn = 0 and ckpmn = 1, or dapmn = 1 and ckpmn = 0.) sip input data output data sop t kcy2 t kl2 t kh2 t sik2 t ksi2 t kso2 sckp caution select the ttl input buffer for the sip pi n and sckp pin and the n-ch open drain output (v dd tolerance) mode for the sop pin by using port input mode register g (pimg) and port output mode register g (pomg). remarks 1. p: csi number (p = 00, 01, 10, 20), m: unit number, n: channel number (mn = 00, 01, 02, 10), g: pim and pom number (g = 0, 1) 2. csi01, csi11 and csi21 cannot communicate at di fferent potential. use other csi for communication at different potential. rl78/g1a 2. electrical specifications page 55 of 76 r01ds0151ej0001 rev.0.01 2011.12.26 under development preliminary document specifications in this document are tentative and subject to change. caution the pins mounted depend on the product. refer to 1.3.1 25-pin products to 1.3.4 64-pin products. (10) communication at different po tential (2.5 v) (simplified i 2 c mode) (1/2) (t a = ? 40 to +85 c, 1.8 v ev dd0 v dd 3.6 v, v ss = ev ss0 = 0 v) parameter symbol conditions min. max. unit 2.7 v ev dd0 3.6 v, 2.3 v v b 2.7 v, c b = 50 pf, r b = 2.7 k 1000 khz 2.7 v ev dd0 3.6 v, 2.3 v v b 2.7 v, c b = 100 pf, r b = 2.7 k 400 khz sclr clock frequency f scl 1.8 v ev dd0 < 3.3 v, 1.6 v v b 2.0 v note 1 , c b = 100 pf, r b = 5.5 k 300 khz 2.7 v ev dd0 3.6 v, 2.3 v v b 2.7 v, c b = 50 pf, r b = 2.7 k 475 ns 2.7 v ev dd0 3.6 v, 2.3 v v b 2.7 v, c b = 100 pf, r b = 2.7 k 1150 ns hold time when sclr = ?l? t low 1.8 v ev dd0 < 3.3 v, 1.6 v v b 2.0 v note 1 , c b = 100 pf, r b = 5.5 k 1550 ns 2.7 v ev dd0 3.6 v, 2.3 v v b 2.7 v, c b = 50 pf, r b = 2.7 k 200 ns 2.7 v ev dd0 3.6 v, 2.3 v v b 2.7 v, c b = 100 pf, r b = 2.7 k 600 ns hold time when sclr = ?h? t high 1.8 v ev dd0 < 3.3 v, 1.6 v v b 2.0 v note 1 , c b = 100 pf, r b = 5.5 k 610 ns ( notes , caution and remarks are listed on the next page.) rl78/g1a 2. electrical specifications page 56 of 76 r01ds0151ej0001 rev.0.01 2011.12.26 under development preliminary document specifications in this document are tentative and subject to change. caution the pins mounted depend on the product. refer to 1.3.1 25-pin products to 1.3.4 64-pin products. (10) communication at different po tential (2.5 v) (simplified i 2 c mode) (2/2) (t a = ? 40 to +85 c, 1.8 v ev dd0 v dd 3.6 v, v ss = ev ss0 = 0 v) parameter symbol conditions min. max. unit 2.7 v ev dd0 3.6 v, 2.3 v v b 2.7 v, c b = 50 pf, r b = 2.7 k 1/f mck + 135 note 2 ns 2.7 v ev dd0 3.6 v, 2.3 v v b 2.7 v, c b = 100 pf, r b = 2.7 k 1/f mck + 190 note 2 ns data setup time (reception) t su:dat 1.8 v ev dd0 < 3.3 v, 1.6 v v b 2.0 v notes 1 , c b = 100 pf, r b = 5.5 k 1/f mck + 190 note 2 ns 2.7 v ev dd0 3.6 v, 2.3 v v b 2.7 v, c b = 50 pf, r b = 2.7 k 0 305 ns 2.7 v ev dd0 3.6 v, 2.3 v v b 2.7 v, c b = 100 pf, r b = 2.7 k 0 355 ns data hold time (transmission) t hd:dat 1.8 v ev dd0 < 3.3 v, 1.6 v v b 2.0 v note 1 , c b = 100 pf, r b = 5.5 k 0 405 ns notes 1. use it with ev dd0 v b . 2. set the f mck value to keep the hold time of sclr = "l" and sclr = "h". caution select the ttl input buffer and the n-ch open drain output (v dd tolerance) mode for the sdar pin and the n-ch open drain output (v dd tolerance) mode for the sclr pin by using port input mode register g (pimg) and port out put mode register g (pomg). ( remarks is listed on the next page.) rl78/g1a 2. electrical specifications page 57 of 76 r01ds0151ej0001 rev.0.01 2011.12.26 under development preliminary document specifications in this document are tentative and subject to change. caution the pins mounted depend on the product. refer to 1.3.1 25-pin products to 1.3.4 64-pin products. simplified i 2 c mode connection diagram (during communication at different potential) user's device sdar sclr sda scl v b r b v b r b rl78/g1a simplified i 2 c mode serial transfer timing (during communication at different potential) sdar t low t high t hd:dat sclr t su:dat 1/f scl caution select the ttl input buffer and the n-ch open drain output (v dd tolerance) mode for the sdar pin and the n-ch open drain output (v dd tolerance) mode for the sclr pin by using port input mode register g (pimg) and port out put mode register g (pomg). remarks 1. r b [ ]:communication line (sdar, sclr) pull-up resistance, c b [f]: communication line (sdar, sclr) load capacitance, v b [v]: communication line voltage 2. r: iic number (r = 00, 01, 10, 20), g: pim, pom number (g = 0, 1) 3. f mck : serial array unit operation clock frequency (operation clock to be set by the cksmn bit of seri al mode register mn (smrmn). m: unit number, n: channel number (mn = 00, 01, 02, 10) 4. v ih and v il below are observation points for the ac characteristics of the serial array unit when communicating at different potentials in simplified i 2 c mode mode. 2.7 v ev dd0 < 3.6 v, 2.3 v v b 2.7 v: v ih = 2.0 v, v il = 0.5 v 1.8 v ev dd0 < 3.3 v, 1.6 v v b 2.0 v: v ih = 1.5 v, v il = 0.32 v rl78/g1a 2. electrical specifications page 58 of 76 r01ds0151ej0001 rev.0.01 2011.12.26 under development preliminary document specifications in this document are tentative and subject to change. caution the pins mounted depend on the product. refer to 1.3.1 25-pin products to 1.3.4 64-pin products. 2.5.2 serial interface iica (t a = ? 40 to +85 c, 1.6 v ev dd0 v dd 3.6 v, v ss = ev ss0 = 0 v) standard mode fast mode fast mode plus parameter symbol conditions min. max. min. max. min. max. unit fast mode plus: f clk 10 mhz 2.7 v ev dd0 3.6 v 0 1000 khz fast mode: f clk 3.5 mhz 1.8 v ev dd0 3.6 v 0 400 khz scla0 clock frequency f scl normal mode: f clk 1 mhz 1.6 v ev dd0 3.6 v 0 100 khz setup time of restart condition t su:sta 4.7 0.6 0.26 s hold time note 1 t hd:sta 4.0 0.6 0.26 s hold time when scla0 = ?l? t low 4.7 1.3 0.5 s hold time when scla0 = ?h? t high 4.0 0.6 0.26 s data setup time (reception) t su:dat 250 100 50 ns data hold time (transmission) note 2 t hd:dat 0 3.45 0 0.9 0 s setup time of stop condition t su:sto 4.0 0.6 0.26 s bus-free time t buf 4.7 1.3 0.5 s notes 1. the first clock pulse is generated after this per iod when the start/restart condition is detected. 2. the maximum value (max.) of t hd:dat is during normal transfer and a wait state is inserted in the ack (acknowledge) timing. remark the maximum value of cb (communication line capa citance) and the value of rb (communication line pull-up resistor) at that time in each mode are as follows. standard mode: c b = 400 pf, r b = 2.7 k fast mode: c b = 320 pf, r b = 1.1 k fast mode plus: c b = 120 pf, r b = 1.1 k iica serial transfer timing t low t low t high t hd:sta stop condition start condition restart condition stop condition t su:dat t su:sta t su:sto t hd:sta t hd:dat scl0 sda0 rl78/g1a 2. electrical specifications page 59 of 76 r01ds0151ej0001 rev.0.01 2011.12.26 under development preliminary document specifications in this document are tentative and subject to change. caution the pins mounted depend on the product. refer to 1.3.1 25-pin products to 1.3.4 64-pin products. 2.5.3 on-chip debug (uart) (t a = ? 40 to +85 c, 1.8 v ev dd0 v dd 3.6 v, v ss = ev ss0 = 0 v) parameter symbol conditions min. typ. max. unit transfer rate 115.2 k 1 m bps rl78/g1a 2. electrical specifications page 60 of 76 r01ds0151ej0001 rev.0.01 2011.12.26 under development preliminary document specifications in this document are tentative and subject to change. caution the pins mounted depend on the product. refer to 1.3.1 25-pin products to 1.3.4 64-pin products. 2.6 analog characteristics 2.6.1 a/d converter characteristics (1) when av ref (+) = av refp /ani0 (adrefp1 = 0, adrefp0 = 1), av ref ( ? ) = av refm /ani1 (adrefm = 1), target ani pin : ani0 to ani12 (supply ani pin to av dd ) (t a = ? 40 to +85 c, 1.6 v v dd 3.6 v, 1.6 v av dd 3.6 v, v ss = 0 v, av ss = 0 v, reference voltage (+) = av refp , reference voltage ( ? ) = av refm = 0 v) parameter symbol conditions min. typ. max. unit 2.4 v av dd 3.6 v 8 12 bit 1.8 v av dd 3.6 v 8 10 note 1 resolution r es 1.6 v av dd 3.6 v 8 note 2 12-bit resolution 2.4 v av dd 3.6 v 6.0 lsb 10-bit resolution 1.8 v av dd 3.6 v 3.5 overall error note 3 ainl 8-bit resolution 1.6 v av dd 3.6 v 1.75 adtyp = 0, 12-bit resolution 2.4 v v dd 3.6 v 3.375 adtyp = 0, 10-bit resolution note 1 1.8 v v dd 3.6 v 6.75 adtyp = 0, 8-bit resolution note 2 1.6 v v dd 3.6 v 13.5 2.4 v v dd 3.6 v 2.5625 1.8 v v dd 3.6 v 5.125 conversion time t conv adtyp = 1, 8-bit resolution 1.6 v v dd 3.6 v 10.25 s 12-bit resolution 2.4 v v dd 3.6 v 4.0 %fsr 10-bit resolution 1.8 v v dd 3.6 v 2.5 zero-scale error notes 3, 4 ezs 8-bit resolution 1.6 v v dd 3.6 v 1.25 12-bit resolution 2.4 v v dd 3.6 v 4.0 %fsr 10-bit resolution 1.8 v v dd 3.6 v 2.5 full-scale error notes 3, 4 efs 8-bit resolution 1.6 v v dd 3.6 v 1.25 12-bit resolution 2.4 v v dd 3.6 v t.b.d. lsb 10-bit resolution 1.8 v v dd 3.6 v t.b.d. integral linearity error note 3 ile 8-bit resolution 1.6 v v dd 3.6 v t.b.d. 12-bit resolution 2.4 v v dd 3.6 v t.b.d. lsb 10-bit resolution 1.8 v v dd 3.6 v t.b.d. differential linearity error note 3 dle 8-bit resolution 1.6 v v dd 3.6 v t.b.d. 2.4 v v dd 3.6 v 2.4 av dd v 1.8 v v dd 3.6 v 1.8 av dd reference voltage (+) av ref(+) = av refp 1.6 v v dd 3.6 v 1.6 av dd reference voltage ( ? ) av ref(-) = av refm ? 0.5 0.3 v v ain 0 av refp v analog input voltage v bgr 2.4 v v dd 3.6 v 1.38 1.45 1.5 v consumption current i adc av dd = 3.6 v 460 1090 a v ref current i avref av refp = 3.6 v 14 25 a notes 1. cannot be used for lower 2 bit of adcr register 2. cannot be used for lower 4 bit of adcr register 3. excludes quantization error ( 1/2 lsb). 4. this value is indicated as a ratio (%fsr) to the full-scale value. caution always use av dd pin with the same potential as the v dd pin. rl78/g1a 2. electrical specifications page 61 of 76 r01ds0151ej0001 rev.0.01 2011.12.26 under development preliminary document specifications in this document are tentative and subject to change. caution the pins mounted depend on the product. refer to 1.3.1 25-pin products to 1.3.4 64-pin products. (2) when av ref (+) = av dd (adrefp1 = 0, adrefp0 = 0), av ref ( ? ) = av ss (adrefm = 0), target ani pin : ani0 to ani12 (supply ani pin to av dd ) (t a = ? 40 to +85 c, 1.6 v v dd 3.6 v, 1.6 v av dd 3.6 v, v ss = 0 v, av ss = 0 v, reference voltage (+) = av refp , reference voltage ( ? ) = av refm = 0 v) parameter symbol conditions min. typ. max. unit 2.4 v av dd 3.6 v 8 12 bit 1.8 v av dd 3.6 v 8 10 note 1 resolution r es 1.6 v av dd 3.6 v 8 note 2 12-bit resolution 2.4 v av dd 3.6 v 9.0 lsb 10-bit resolution 1.8 v av dd 3.6 v 5.0 overall error note 3 ainl 8-bit resolution 1.6 v av dd 3.6 v 2.5 adtyp = 0, 12-bit resolution 2.4 v v dd 3.6 v 3.375 adtyp = 0, 10-bit resolution note 1 1.8 v v dd 3.6 v 6.75 adtyp = 0, 8-bit resolution note 2 1.6 v v dd 3.6 v 13.5 2.4 v v dd 3.6 v 2.5625 1.8 v v dd 3.6 v 5.125 conversion time t conv adtyp = 1, 8-bit resolution 1.6 v v dd 3.6 v 10.25 s 12-bit resolution 2.4 v v dd 3.6 v 7.0 %fsr 10-bit resolution 1.8 v v dd 3.6 v 3.75 zero-scale error notes 3, 4 ezs 8-bit resolution 1.6 v v dd 3.6 v 2.0 12-bit resolution 2.4 v v dd 3.6 v 7.0 %fsr 10-bit resolution 1.8 v v dd 3.6 v 3.75 full-scale error notes 3, 4 efs 8-bit resolution 1.6 v v dd 3.6 v 2.0 12-bit resolution 2.4 v v dd 3.6 v t.b.d. lsb 10-bit resolution 1.8 v v dd 3.6 v t.b.d. integral linearity error note 3 ile 8-bit resolution 1.6 v v dd 3.6 v t.b.d. 12-bit resolution 2.4 v v dd 3.6 v t.b.d. lsb 10-bit resolution 1.8 v v dd 3.6 v t.b.d. differential linearity error note 3 dle 8-bit resolution 1.6 v v dd 3.6 v t.b.d. reference voltage (+) av refp = av dd 1.6 3.6 v reference voltage ( ? ) av refm = av ss ? 0.5 0.3 v v ain 0 av refp v analog input voltage v bgr 2.4 v v dd 3.6 v 1.38 1.45 1.5 v consumption current i adc av dd = 3.6 v 460 1090 a v ref current i avref av refp = 3.6 v 14 25 a notes 1. cannot be used for lower 2 bit of adcr register 2. cannot be used for lower 4 bit of adcr register 3. excludes quantization error ( 1/2 lsb). 4. this value is indicated as a ratio (%fsr) to the full-scale value. caution always use av dd pin with the same potential as the v dd pin. rl78/g1a 2. electrical specifications page 62 of 76 r01ds0151ej0001 rev.0.01 2011.12.26 under development preliminary document specifications in this document are tentative and subject to change. caution the pins mounted depend on the product. refer to 1.3.1 25-pin products to 1.3.4 64-pin products. (3) when av ref (+) = av refp /ani0 (adrefp1 = 0, adrefp0 = 1), av ref ( ? ) = av refm /ani1 (adrefm = 1), target ani pin : ani16 to ani30 (supply ani pin to ev dd0 ) (t a = ? 40 to +85 c, 1.6 v ev dd0 v dd 3.6 v, 1.6 v av dd 3.6 v, v ss = ev ss0 = 0 v, av ss = 0 v, reference voltage (+) = av refp , reference voltage ( ? ) = av refm = 0 v) parameter symbol conditions min. typ. max. unit 2.4 v av dd 3.6 v 8 12 bit 1.8 v av dd 3.6 v 8 10 note 1 resolution r es 1.6 v av dd 3.6 v 8 note 2 12-bit resolution 2.4 v av dd 3.6 v 9.0 lsb 10-bit resolution 1.8 v av dd 3.6 v 5.0 overall error note 3 ainl 8-bit resolution 1.6 v av dd 3.6 v 2.5 adtyp = 0, 12-bit resolution 2.4 v v dd 3.6 v 4.125 adtyp = 0, 10-bit resolution note 1 1.8 v v dd 3.6 v 9.5 adtyp = 0, 8-bit resolution note 2 1.6 v v dd 3.6 v 57.5 2.4 v v dd 3.6 v 3.3125 1.8 v v dd 3.6 v 7.875 conversion time t conv adtyp = 1, 8-bit resolution 1.6 v v dd 3.6 v 54.25 s 12-bit resolution 2.4 v v dd 3.6 v 7.0 %fsr 10-bit resolution 1.8 v v dd 3.6 v 3.75 zero-scale error notes 3, 4 ezs 8-bit resolution 1.6 v v dd 3.6 v 2.0 12-bit resolution 2.4 v v dd 3.6 v 7.0 %fsr 10-bit resolution 1.8 v v dd 3.6 v 3.75 full-scale error notes 3, 4 efs 8-bit resolution 1.6 v v dd 3.6 v 2.0 12-bit resolution 2.4 v v dd 3.6 v t.b.d. lsb 10-bit resolution 1.8 v v dd 3.6 v t.b.d. integral linearity error note 3 ile 8-bit resolution 1.6 v v dd 3.6 v t.b.d. 12-bit resolution 2.4 v v dd 3.6 v t.b.d. lsb 10-bit resolution 1.8 v v dd 3.6 v t.b.d. differential linearity error note 3 dle 8-bit resolution 1.6 v v dd 3.6 v t.b.d. 2.4 v v dd 3.6 v 2.4 av dd v 1.8 v v dd 3.6 v 1.8 av dd reference voltage (+) av ref(+) = av refp 1.6 v v dd 3.6 v 1.6 av dd reference voltage ( ? ) av ref((-) = av refm ? 0.5 0.3 v v ain 0 av refp v analog input voltage v bgr 2.4 v v dd 3.6 v 1.38 1.45 1.5 v consumption current i adc av dd = 3.6 v 400 950 a v ref current i avref av refp = 3.6 v 14 25 a notes 1. cannot be used for lower 2 bit of adcr register 2. cannot be used for lower 4 bit of adcr register 3. excludes quantization error ( 1/2 lsb). 4. this value is indicated as a ratio (%fsr) to the full-scale value. caution always use av dd pin with the same potential as the v dd pin. rl78/g1a 2. electrical specifications page 63 of 76 r01ds0151ej0001 rev.0.01 2011.12.26 under development preliminary document specifications in this document are tentative and subject to change. caution the pins mounted depend on the product. refer to 1.3.1 25-pin products to 1.3.4 64-pin products. (4) when av ref (+) = av dd (adrefp1 = 0, adrefp0 = 0), av ref ( ? ) = av ss (adrefm = 0), target ani pin : ani16 to ani30 (supply ani pin to ev dd0 ) (t a = ? 40 to +85 c, 1.6 v ev dd0 v dd0 3.6 v, 1.6 v av dd 3.6 v, v ss = ev ss0 = 0 v, av ss = 0 v, reference voltage (+) = av dd , reference voltage ( ? ) = av ss = 0 v) parameter symbol conditions min. typ. max. unit 2.4 v av dd 3.6 v 8 12 bit 1.8 v av dd 3.6 v 8 10 note 1 resolution r es 1.6 v av dd 3.6 v 8 note 2 12-bit resolution 2.4 v av dd 3.6 v 14.0 lsb 10-bit resolution 1.8 v av dd 3.6 v 7.5 overall error note 3 ainl 8-bit resolution 1.6 v av dd 3.6 v 3.75 adtyp = 0, 12-bit resolution 2.4 v v dd 3.6 v 4.125 s adtyp = 0, 10-bit resolution note 1 1.8 v v dd 3.6 v 9.5 adtyp = 0, 8-bit resolution note 2 1.6 v v dd 3.6 v 57.5 2.4 v v dd 3.6 v 3.3125 s 1.8 v v dd 3.6 v 7.875 conversion time t conv adtyp = 1, 8-bit resolution 1.6 v v dd 3.6 v 54.25 12-bit resolution 2.4 v v dd 3.6 v 9.0 %fsr 10-bit resolution 1.8 v v dd 3.6 v 5.0 zero-scale error notes 3, 4 ezs 8-bit resolution 1.6 v v dd 3.6 v 2.5 12-bit resolution 2.4 v v dd 3.6 v 9.0 %fsr 10-bit resolution 1.8 v v dd 3.6 v 5.0 full-scale error notes 3, 4 efs 8-bit resolution 1.6 v v dd 3.6 v 2.5 12-bit resolution 2.4 v v dd 3.6 v t.b.d. lsb 10-bit resolution 1.8 v v dd 3.6 v t.b.d. integral linearity error note 3 ile 8-bit resolution 1.6 v v dd 3.6 v t.b.d. 12-bit resolution 2.4 v v dd 3.6 v t.b.d. lsb 10-bit resolution 1.8 v v dd 3.6 v t.b.d. differential linearity error note 3 dle 8-bit resolution 1.6 v v dd 3.6 v t.b.d. reference voltage (+) av ref(+) = av dd 1.6 3.6 v reference voltage ( ? ) av ref(-) = av ss ? 0.5 0.3 v v ain 0 av refp v analog input voltage v bgr 2.4 v v dd 3.6 v 1.38 1.45 1.5 v consumption current i adc av dd = 3.6 v 400 950 a v ref current i avref av refp = 3.6 v 14 25 a notes 1. cannot be used for lower 2 bit of adcr register 2. cannot be used for lower 4 bit of adcr register 3. excludes quantization error ( 1/2 lsb). 4. this value is indicated as a ratio (%fsr) to the full-scale value. caution always use av dd pin with the same potential as the v dd pin. rl78/g1a 2. electrical specifications page 64 of 76 r01ds0151ej0001 rev.0.01 2011.12.26 under development preliminary document specifications in this document are tentative and subject to change. caution the pins mounted depend on the product. refer to 1.3.1 25-pin products to 1.3.4 64-pin products. (5) when av ref (+) = internal reference voltage (1. 45 v) (adrefp1 = 1, adrefp0 = 0), av ref ( ? ) = av ss (adrefm = 0), target ani pin : ani0 to ani12, ani16 to ani30 (t a = ? 40 to +85 c, 1.6 v ev dd0 v dd 3.6 v, 1.6 v av dd 3.6 v, v ss = ev ss0 = 0 v, av ss0 = 0 v, reference voltage (+) = internal reference voltage, reference voltage ( ? ) = av ss = 0 v) parameter symbol conditions min. typ. max. unit resolution r es 8 bit conversion time t conv 8-bit resolution 16 s zero-scale error notes 1, 2 ezs 8-bit resolution 2.5 %fsr integral linearity error note 1 ile 8-bit resolution t.b.d. lsb differential linearity error note 1 dle 8-bit resolution t.b.d. lsb reference voltage (+) av ref(+) = internal reference voltage 1.38 1.45 1.5 v reference voltage ( ? ) av ref(-) = av ss ? 0.5 0.3 v v ain 0 av refp v analog input voltage v bgr conversion prohibit v consumption current i adc av dd = 3.6 v 400 950 a v ref current i avref 75 a notes 1. excludes quantization error ( 1/2 lsb). 2. this value is indicated as a ratio (%fsr) to the full-scale value. caution always use av dd pin with the same potential as the v dd pin. rl78/g1a 2. electrical specifications page 65 of 76 r01ds0151ej0001 rev.0.01 2011.12.26 under development preliminary document specifications in this document are tentative and subject to change. caution the pins mounted depend on the product. refer to 1.3.1 25-pin products to 1.3.4 64-pin products. 2.6.2 temperature sensor characteristics (t a = ? 40 to +85 c, 2.4 v ev dd0 v dd 3.6 v, v ss = ev ss0 = 0 v) parameter symbol conditions min. typ. max. unit temperature sensor output voltage v tmps25 setting ads register = 80h, t a = +25 c 1.05 v reference output voltage v const setting ads register = 81h 1.38 1.45 1.5 v temperature coefficient f vtmps temperature sensor that depends on the temperature ? 3.6 mv/c operation stabilization wait time t amp 2 s 2.6.3 por circuit characteristics (t a = ? 40 to +85 c, v ss = 0 v) parameter symbol conditions min. typ. max. unit v por power supply rise time 1.48 1.51 1.54 v detection voltage v pdr power supply fall time 1.47 1.50 1.53 v minimum pulse width t pw 300 s detection delay time 350 s rl78/g1a 2. electrical specifications page 66 of 76 r01ds0151ej0001 rev.0.01 2011.12.26 under development preliminary document specifications in this document are tentative and subject to change. caution the pins mounted depend on the product. refer to 1.3.1 25-pin products to 1.3.4 64-pin products. 2.6.4 lvd circuit characteristics lvd detection voltage of reset mode and interrupt mode (t a = ? 40 to +85 c, v pdr ev dd0 v dd 3.6 v, v ss = ev ss0 = 0 v) parameter symbol conditions min. typ. max. unit power supply rise time 3.07 3.13 3.19 v v lvd2 power supply fall time 3.00 3.06 3.12 v power supply rise time 2.96 3.02 3.08 v v lvd3 power supply fall time 2.90 2.96 3.02 v power supply rise time 2.86 2.92 2.97 v v lvd4 power supply fall time 2.80 2.86 2.91 v power supply rise time 2.76 2.81 2.87 v v lvd5 power supply fall time 2.70 2.75 2.81 v power supply rise time 2.66 2.71 2.76 v v lvd6 power supply fall time 2.60 2.65 2.70 v power supply rise time 2.56 2.61 2.66 v v lvd7 power supply fall time 2.50 2.55 2.60 v power supply rise time 2.45 2.50 2.55 v v lvd8 power supply fall time 2.40 2.45 2.50 v power supply rise time 2.05 2.09 2.13 v v lvd9 power supply fall time 2.00 2.04 2.08 v power supply rise time 1.94 1.98 2.02 v v lvd10 power supply fall time 1.90 1.94 1.98 v power supply rise time 1.84 1.88 1.91 v v lvd11 power supply fall time 1.80 1.84 1.87 v power supply rise time 1.74 1.77 1.81 v v lvd12 power supply fall time 1.70 1.73 1.77 v power supply rise time 1.64 1.67 1.70 v detection voltage supply voltage level v lvd13 power supply fall time 1.60 1.63 1.66 v minimum pulse width t lw 300 s detection delay time 300 s remark v lvd(n ? 1) > v lvdn : n = 3 to 13 rl78/g1a 2. electrical specifications page 67 of 76 r01ds0151ej0001 rev.0.01 2011.12.26 under development preliminary document specifications in this document are tentative and subject to change. caution the pins mounted depend on the product. refer to 1.3.1 25-pin products to 1.3.4 64-pin products. lvd detection voltage of interrupt & reset mode (t a = ? 40 to +85 c, v pdr ev dd0 v dd 3.6 v, v ss = ev ss0 = 0 v) parameter symbol conditions min. typ. max. unit v lvd13 v poc0 , v poc1 , v poc2 = 0, 0, 0, falling reset voltage: 1.6 v 1.60 1.63 1.66 v rising release reset voltage 1.74 1.77 1.81 v v lvd12 lvis0, lvis1 = 1, 0 (+0.1 v) falling interrupt voltage 1.70 1.73 1.77 v rising release reset voltage 1.84 1.88 1.91 v v lvd11 lvis0, lvis1 = 0, 1 (+0.2 v) falling interrupt voltage 1.80 1.84 1.87 v rising release reset voltage 2.86 2.92 2.97 v v lvd4 lvis0, lvis1 = 0, 0 (+1.2 v) falling interrupt voltage 2.80 2.86 2.91 v v lvd11 v poc0 , v poc1 , v poc2 = 0, 0, 1, falling reset voltage: 1.8 v 1.80 1.84 1.87 v rising release reset voltage 1.94 1.98 2.02 v v lvd10 lvis0, lvis1 = 1, 0 (+0.1 v) falling interrupt voltage 1.90 1.94 1.98 v rising release reset voltage 2.05 2.09 2.13 v v lvd9 lvis0, lvis1 = 0, 1 (+0.2 v) falling interrupt voltage 2.00 2.04 2.08 v rising release reset voltage 3.07 3.13 3.19 v v lvd2 lvis0, lvis1 = 0, 0 (+1.2 v) falling interrupt voltage 3.00 3.06 3.12 v v lvd8 v poc0 , v poc1 , v poc2 = 0, 1, 0, falling reset voltage: 2.4 v 2.40 2.45 2.50 v rising release reset voltage 2.56 2.61 2.66 v v lvd7 lvis0, lvis1 = 1, 0 (+0.1 v) falling interrupt voltage 2.50 2.55 2.60 v rising release reset voltage 2.66 2.71 2.76 v v lvd6 lvis0, lvis1 = 0, 1 (+0.2 v) falling interrupt voltage 2.60 2.65 2.70 v v lvd5 v poc0 , v poc1 , v poc2 = 0, 1, 1, falling reset voltage: 2.7 v 2.70 2.75 2.81 v rising release reset voltage 2.86 2.92 2.97 v v lvd4 lvis0, lvis1 = 1, 0 (+0.1 v) falling interrupt voltage 2.80 2.86 2.91 v rising release reset voltage 2.96 3.02 3.08 v interrupt and reset mode v lvd3 lvis0, lvis1 = 0, 1 (+0.2 v) falling interrupt voltage 2.90 2.96 3.02 v rl78/g1a 2. electrical specifications page 68 of 76 r01ds0151ej0001 rev.0.01 2011.12.26 under development preliminary document specifications in this document are tentative and subject to change. caution the pins mounted depend on the product. refer to 1.3.1 25-pin products to 1.3.4 64-pin products. supply voltage rise time (t a = ? 40 to +85 c, v ss = 0 v) parameter symbol conditions min. typ. max. unit maximum time to rise to 1.6 v (v dd (min.)) note (v dd : 0 v 1.6 v) t pup1 when reset input is not used 3.2 ms note make sure to raise the power s upply in a shorter time than this. supply voltage rise time timing ? when reset pin input is not used supply voltage (v dd ) time 1.6 v 0 v por internal signal t pup1 rl78/g1a 2. electrical specifications page 69 of 76 r01ds0151ej0001 rev.0.01 2011.12.26 under development preliminary document specifications in this document are tentative and subject to change. caution the pins mounted depend on the product. refer to 1.3.1 25-pin products to 1.3.4 64-pin products. 2.7 data memory stop mode low supply voltage data retention characteristics (t a = ? 40 to +85 c) parameter symbol conditions min. typ. max. unit data retention supply voltage v dddr 1.47 note 3.6 v note the value depends on the por detec tion voltage. when the voltage dr ops, the data is retained before a por reset is effected, but data is not re tained when a por reset is effected. v dd stop instruction execution standby release signal (interrupt request) stop mode data retention mode v dddr operation mode 2.8 flash memory programming characteristics (t a = ? 40 to +85 c, 1.8 v ev dd0 v dd 3.6 v, v ss = ev ss0 = 0 v) parameter symbol conditions min. typ. max. unit cpu/peripheral hardware clock frequency f clk 1.8 v v dd 3.6 v 1 32 mhz number of code flash rewrites retained for 20 years (self/serial programming) note 1,000 retained for 1 years (self/serial programming) note 1,000,000 number of data flash rewrites c erwr 1 erase + 1 write after the erase is regarded as 1 rewrite. the retaining years are until next rewrite after the rewrite. retained for 5 years (self/serial programming) note 100,000 times note when using flash memory programmer and renesas electronics self programming library remark when updating data multiple times, use the flash memory as one for updating data. rl78/g1a 2. electrical specifications page 70 of 76 r01ds0151ej0001 rev.0.01 2011.12.26 under development preliminary document specifications in this document are tentative and subject to change. caution the pins mounted depend on the product. refer to 1.3.1 25-pin products to 1.3.4 64-pin products. 2.9 timing specs for switching modes (t a = ? 40 to +85 c, 1.8 v ev dd0 v dd 3.6 v, v ss = ev ss0 = 0 v) parameter symbol conditions min. typ. max. unit how long from when a pin reset ends until the initial communication settings are specified t suinit por and lvd reset must end before the pin reset ends. 100 ms how long from when the tool0 pin is placed at the low level until a pin reset ends t su por and lvd reset must end before the pin reset ends. 10 s how long the tool0 pin must be kept at the low level after a reset ends t hd por and lvd reset must end before the pin reset ends. 1 ms <1> <2> <3> reset tool0 t suinit t hd + software processing time <4> t su <1> the low level is input to the tool0 pin. <2> the pins reset ends (por and lvd reset must end before the pin reset ends.). <3> the tool0 pin is set to the high level. <4> setting of the flash memory programmi ng mode by uart reception and complete the baud rate setting. remark t suinit : the segment shows that it is necessary to finish specifying the initial communication settings within 100 ms from when the external and internal resets end. t su : how long from when the tool0 pin is placed at the low level until a pin reset ends t hd : how long to keep the tool0 pin at the low level from when the external and internal resets end rl78/g1a 3. package drawings page 71 of 76 r01ds0151ej0001 rev.0.01 2011.12.26 under development preliminary document specifications in this document are tentative and subject to change. 3. package drawings 3.1 25-pin products r5f10e8aala, r5f10e8cala, r5f10e8dala, r5f10e8eala 25-pin plastic flga (3x3) p25fc-50-2n2-1 (aperture of solder resist) item dimensions d e w e a b x y y1 zd ze 3.00 0.10 3.00 0.10 0.05 0.20 0.69 0.07 0.0 8 0.50 0.24 0.05 (u n it:mm) 0.20 0.50 0.50 s y1 s a s detail of c part y s x 21x b ab m e b 0.34 0.05 0.43 0.05 0.50 0.05 0.365 0.05 r0.17 0.05 r0.165 0.05 r0.215 0.05 0.365 0.05 0.50 0.05 0.33 0.05 0.43 0.05 s w b zd ze i n dex mark b c a s w a d e 2.27 2.27 detail of d part d 1 2 edcba 3 4 5 (la n d pad) r0.12 0.05 0.33 0.05 i n dex mark 2010 renesas electronics corporation. all ri g hts reserved. rl78/g1a 3. package drawings page 72 of 76 r01ds0151ej0001 rev.0.01 2011.12.26 under development preliminary document specifications in this document are tentative and subject to change. 3.2 32-pin products r5f10ebaana, r5f10ebcana, r5f10ebdana, r5f10ebeana 32-pin plastic wqfn(5x5) s y e lp s x ba b m a d e 24 16 17 8 9 1 32 a s b a d e a b e lp x y 5.00 0.05 0.50 0.05 0.05 5.00 0.05 0.75 0.05 0.25 0.05 + 0.07 0.40 0.10 p32k8-50-3b4-2 s d2 e2 (unit:mm) item dimensions 25 detail of a part ? exposed die pad item d2 e2 a min nom max 3.45 3.50 exposed die pad variations 3.55 min nom max 3.45 3.50 3.55 rl78/g1a 3. package drawings page 73 of 76 r01ds0151ej0001 rev.0.01 2011.12.26 under development preliminary document specifications in this document are tentative and subject to change. 3.3 48-pin products r5f10egaafb, r5f10egcafb, r5f10egdafb, R5F10EGEAFB s y e s x b m l c lp hd he zd ze l1 a1 a2 a d e a3 s 0.145 + 0.055 ? 0.045 (unit:mm) item dimensions d e hd he a a1 a2 a3 7.00 0.20 7.00 0.20 9.00 0.20 9.00 0.20 1.60 max. 0.10 0.05 1.40 0.05 0.25 c e x y zd ze 0.50 0.08 0.08 0.75 0.75 l lp l1 0.50 0.60 0.15 1.00 0.20 p48ga-50-8eu 3 + 5 ? 3 note each lead centerline is located within 0.08 mm of its true position at maximum material condition. detail of lead end 48-pin plastic lqfp (fine pitch)(7x7) 0.22 0.05 b 12 24 1 48 13 25 37 36 rl78/g1a 3. package drawings page 74 of 76 r01ds0151ej0001 rev.0.01 2011.12.26 under development preliminary document specifications in this document are tentative and subject to change. r5f10egaana, r5f10egcana, r5f10egdana, r5f10egeana 48-pin plastic wqfn(7x7) detail of a part s y e lp s x ba b m a d e 36 37 24 25 12 13 1 48 a s b a item dimensions d e a b e lp x y 7.00 0.05 0.50 0.05 0.05 7.00 0.05 0.75 0.05 0.25 0.05 + 0.07 0.40 0.10 (unit:mm ) p48k8-50-5b4-3 s d2 e2 ? exposed die pad item d2 e2 a min nom max 5.45 5.50 exposed die pad variations 5.55 min nom max 5.45 5.50 5.55 rl78/g1a 3. package drawings page 75 of 76 r01ds0151ej0001 rev.0.01 2011.12.26 under development preliminary document specifications in this document are tentative and subject to change. 3.4 64-pin products r5f10elcafb, r5f10eldafb, r5f10eleafb s y e s x b m l c lp hd he zd ze l1 a1 a2 a d e a3 s 0.145 + 0.055 ? 0.045 (unit:mm) item dimensions d e hd he a a1 a2 a3 10.00 0.20 10.00 0.20 12.00 0.20 12.00 0.20 1.60 max. 0.10 0.05 1.40 0.05 0.25 c e x y zd ze 0.50 0.08 0.08 1.25 1.25 l lp l1 0.50 0.60 0.15 1.00 0.20 p64gb-50-ueu-1 3 + 5 ? 3 note each lead centerline is located within 0.08 mm of its true position at maximum material condition. detail of lead end 0.22 0.05 b 16 32 1 64 17 33 49 48 64-pin plastic lqfp(fine pitch)(10x10) rl78/g1a 3. package drawings page 76 of 76 r01ds0151ej0001 rev.0.01 2011.12.26 under development preliminary document specifications in this document are tentative and subject to change. r5f10elcabg, r5f10eldabg, r5f10eleabg item dimensions d e w a a1 a2 e 4.00 0.10 4.00 0.10 0.40 0.05 0.08 0.20 0.60 0.60 0.15 0.20 0.05 0.05 0.89 0.10 0.69 p64f1-40-aa2-1 0.25 (unit:mm) x y y1 zd ze b zd ze a index mark a2 a1 e s w a s wb b a s y s y1 s s x bab m 8 7 6 5 4 3 2 1 a b c d e f g h d e index mark 2011 renesas electronics corporation. all rights reserved. 64-pin plastic fbga (4x4) all trademarks and registered trademarks are t he property of their respective owners. c - 1 revision history rl78/g1a data sheet description rev. date page summary 0.01 dec 26, 2011 - first edition issued superflash is a registered trademark of silicon storage technology, inc. in several countries including the united states and japan. caution: this product uses superflash ? technology licensed from silicon storage technology, inc. notes for cmos devices (1) voltage application waveform at input pin: waveform distortion due to input noise or a reflected wave may cause malfunction. if the input of the cmos device stays in the area between vil (max) and vih (min) due to noise, etc ., the device may malfunction. take care to prevent chattering noise from entering the device when the input level is fixed, and also in the transition period when the input level passes through the area between vil (max) and vih (min). (2) handling of unused input pins: unconnected cmos device inputs can be cause of malfunction. if an input pin is unconnected, it is po ssible that an internal input level may be generated due to noise, etc., causing malfunction. cmos devices behave different ly than bipolar or nmos dev ices. input levels of cmos devices must be fixed high or low by using pull-up or pull-down circuitry. each unused pin should be connected to vdd or gnd via a resistor if there is a possibility that it will be an output pin. all handling related to unused pins must be judged separately for each device and according to related specifications governing the device. (3) precaution against esd: a strong electric fi eld, when exposed to a mos device, can cause destruction of the gate oxide and ultimately degrade t he device operation. steps must be taken to stop generation of static elec tricity as much as possible, and quickly dissipate it when it has occurred. environmental control must be adequ ate. when it is dry, a humidifier should be used. it is recommended to avoid using insulators that easily build up static electricity. semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. all test and measurement tools including work benches and floors should be gr ounded. the operator should be grounded using a wrist strap. semiconductor devices must not be touched with bare hands. similar precautions need to be taken for pw boards with mounted semiconductor devices. (4) status before initialization: power-on does not necessarily define the in itial status of a mos device. immediately after the power source is turned on, devices with reset functions have not yet been initialized. hence, power-on does no t guarantee output pin levels, i/o settings or contents of registers. a device is not initialized until the re set signal is received. a reset operation must be ex ecuted immediately after power-on for devices with reset functions. (5) power on/off sequence: in the case of a device that uses different power supplies for the internal operation and external interface, as a rule, switch on the external power supply after switching on the internal power supply. when switching the power supply off, as a rule, switch off the exte rnal power su pply and then the internal power supply. use of the reverse powe r on/off sequences may result in the application of an overvoltage to the internal elements of the device, causing malfunction and degradation of internal elements due to the passage of an abnormal current. the corre ct power on/off sequence must be judged separately for each device and according to related sp ecifications governing the device. (6) input of signal during power off state : do not input signals or an i/o pull-up power supply while the device is not powered. t he current injection that results from input of such a signal or i/o pull-up power supply may cause malfunction and the abnormal cu rrent that passes in the device at this time may cause degradation of internal elemen ts. input of signals during the power off state must be judged separately for each device and according to re lated specifications governing the device. notice 1. all information included in this document is current as of the date this document is issued. such information, however, is s ubject to change without any prior notice. before purchasing or using any renesas electronics products listed herein, please confirm the latest product information with a renesas electronics sales office. also , please pay regular and careful attention to additional and different information to be disclosed by renesas electronics such as that disclosed through our website. 2. renesas electronics does not assume any liability for infringement of patents, copyrights, or other intellectual property ri ghts of third parties by or arising from the use of renesas electronics products or technical information described in this document. no license, express, implied or otherwise, is granted hereby under any paten ts, copyrights or other intellectual property rights of renesas electronics or others. 3. you should not alter, modify, copy, or otherwise misappropriate any renesas electronics product, whether in whole or in part . 4. descriptions of circuits, software and other related information in this document are provided only to illustrate the operat ion of semiconductor products and application examples. you are fully responsible for the incorporation of these circuits, software, and information in the design of your equipment. renesas electronics assumes no responsibility for any losses incurred by you or third parties arising from the use of these circuits, software, or information. 5. when exporting the products or technology described in this document, you should comply with the applicable export control l aws and regulations and follow the procedures required by such laws and regulations. you should not use renesas electronics products or the technology described in this document for any purpose rela ting to military applications or use by the military, including but not limited to the development of weapons of mass destruction. renesas electronics products and technology may not be used for or incorporate d into any products or systems whose manufacture, use, or sale is prohibited under any applicable domestic or foreign laws or regulations. 6. renesas electronics has used reasonable care in preparing the information included in this document, but renesas electronics does not warrant that such information is error free. renesas electronics assumes no liability whatsoever for any damages incurred by you resulting from errors in or omissions from the information incl uded herein. 7. renesas electronics products are classified according to the following three quality grades: "standard", "high quality", an d "specific". the recommended applications for each renesas electronics product depends on the product's quality grade, as indicated below. you must check the quality grade of each renesas electronics produ ct before using it in a particular application. you may not use any renesas electronics product for any application categorized as "specific" without the prior written consent of renesas electronics. fu rther, you may not use any renesas electronics product for any application for which it is not intended without the prior written consent of renesas electronics. renesas electronics shall not be in any way liable for any damages or losses incurred by you or third parties arising from the use of any renesas electronics product for an application categorized as "specific" or for which the product is not intended wh ere you have failed to obtain the prior written consent of renesas electronics. the quality grade of each renesas electronics product is "standard" unless otherwise expressly specified in a renesas electroni cs data sheets or data books, etc. "standard": computers; office equipment; communications equipment; test and measurement equipment; audio and visual equipment ; home electronic appliances; machine tools; personal electronic equipment; and industrial robots. "high quality": transportation equipment (automobiles, trains, ships, etc.); traffic control systems; anti-disaster systems; anti-crime systems; safety equipment; and medical equipment not specifically designed for life support. "specific": aircraft; aerospace equipment; submersible repeaters; nuclear reactor control systems; medical equipment or syst ems for life support (e.g. artificial life support devices or systems), surgical implantations, or healthcare intervention (e.g. excision, etc.), and any other applications or purposes that pose a direct thr eat to human life. 8. you should use the renesas electronics products described in this document within the range specified by renesas electronics , especially with respect to the maximum rating, operating supply voltage range, movement power voltage range, heat radiation characteristics, installation and other product characteristics. renesas el ectronics shall have no liability for malfunctions or damages arising out of the use of renesas electronics products beyond such specified ranges. 9. although renesas electronics endeavors to improve the quality and reliability of its products, semiconductor products have s pecific characteristics such as the occurrence of failure at a certain rate and malfunctions under certain use conditions. further, renesas electronics products are not subject to radiation resistance design . please be sure to implement safety measures to guard them against the possibility of physical injury, and injury or damage caused by fire in the event of the failure of a renesas electronics produc t, such as safety design for hardware and software including but not limited to redundancy, fire control and malfunction prevention, appropriate treatment for aging degradation or any other appropriate measu res. because the evaluation of microcomputer software alone is very difficult, please evaluate the safety of the final products or system manufactured by you. 10. please contact a renesas electronics sales office for details as to environmental matters such as the environmental compati bility of each renesas electronics product. please use renesas electronics products in compliance with all applicable laws and regulations that regulate the inclusion or use of controlled substances, in cluding without limitation, the eu rohs directive. renesas electronics assumes no liability for damages or losses occurring as a result of your noncompliance with applicable laws and regulations. 11. this document may not be reproduced or duplicated, in any form, in whole or in part, without prior written consent of renes as electronics. 12. please contact a renesas electronics sales office if you have any questions regarding the information contained in this doc ument or renesas electronics products, or if you have any other inquiries. (note 1) "renesas electronics" as used in this document means renesas electronics corporation and also includes its majority-o wned subsidiaries. (note 2) "renesas electronics product(s)" means any product developed or manufactured by or for renesas electronics. http://www.renesas.com refer to "http://www.renesas.com/" for the latest and detailed information. renesas electronics america inc. 2880 scott boulevard santa clara, ca 95050-2554, u.s.a. tel: +1-408-588-6000, fax: +1-408-588-6130 renesas electronics canada limited 1101 nicholson road, newmarket, ontario l3y 9c3, canada tel: +1-905-898-5441, fax: +1-905-898-3220 renesas electronics europe limited dukes meadow, millboard road, bourne end, buckinghamshire, sl8 5fh, u.k tel: +44-1628-585-100, fax: +44-1628-585-900 renesas electronics europe gmbh arcadiastrasse 10, 40472 dsseldorf, germany tel: +49-211-65030, fax: +49-211-6503-1327 renesas electronics (china) co., ltd. 7th floor, quantum plaza, no.27 zhichunlu haidian district, beijing 100083, p.r.china tel: +86-10-8235-1155, fax: +86-10-8235-7679 renesas electronics (shanghai) co., ltd. unit 204, 205, azia center, no.1233 lujiazui ring rd., pudong district, shanghai 200120, china tel: +86-21-5877-1818, fax: +86-21-6887-7858 / -7898 renesas electronics hong kong limited unit 1601-1613, 16/f., tower 2, grand century place, 193 prince edward road west, mongkok, kowloon, hong kong tel: +852-2886-9318, fax: +852 2886-9022/9044 renesas electronics taiwan co., ltd. 7f, no. 363 fu shing north road taipei, taiwan tel: +886-2-8175-9600, fax: +886 2-8175-9670 renesas electronics singapore pte. ltd. 1 harbourfront avenue, #06-10, keppel bay tower, singapore 098632 tel: +65-6213-0200, fax: +65-6278-8001 renesas electronics malaysia sdn.bhd. unit 906, block b, menara amcorp, amcorp trade centre, no. 18, jln persiaran barat, 46050 petaling jaya, selangor darul ehsan, malaysia tel: +60-3-7955-9390, fax: +60-3-7955-9510 renesas electronics korea co., ltd. 11f., samik lavied' or bldg., 720-2 yeoksam-dong, kangnam-ku, seoul 135-080, korea tel: +82-2-558-3737, fax: +82-2-558-5141 sales offices ? 2011 renesas electronics corporation. all rights reserved. colophon 1.0 |
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